Hi all,
I am new to this forum and just started to discover and utilize Spartan Edge Accelerator.
Thus I found out (the hard way) that the pin order of the (6 pin) JTAG connector unfortunately does not match the established pinning as I know it (referring to debug interfaces from Digilent, e.g. HS1; HS2, and other boards with Xilinx FPGAs).
SEA-S7 HS1
VDD VDD
GND GND
TMS TCK
TCK TDO
TDO TDI
TDI TMS
Of course this can be fixed with a small DIY adapter, but maybe if a redesign is done at some point in time IMHO it would be nice to change this according to the “standard”.