The sampling speed of 72 Mbps and the 8 MHz bandwidth seems rather incompatible. Is this beacuse the 32 MHz bandwidth has been divided by 4 to give 8 MHz by channel? If so, can I disable 3 of the channels and allow the full 32 MHz bandwidth on a single channel. The scope is rather limtied for RF work and I am rather disappointed when i received it that its actual bandwidth is so low.
No, the bandwidth is not divided and only 2 of the channels are analog anyway.
72 MSps sampling and the ~12 MHz bandwidth make perfect sense. You wouldn’t be able to get good waveforms higher than that anyway (only 6 samples per cycle), and this way there is no risk of aliasing.
You can use the interlaced mode on a single channel to achieve 144 MSps sampling, but that doesn’t change the analog bandwidth, just gives more accurate waveform.
How can be used 144MS/s ?
While technically possible and attempts have been made, the 144Ms/sec function has
never to my knowledge been properly implemented.
In theory the way it works is by feeding one of the channels to both A and B inputs
of the ADC. The channel B clock is made out of phase (180 degrees from the
channel A clock). This way you get another sample of the same signal a half clock
sample later fed into channel B. The software then sequences the A and B outputs
to effectively get 144 M samples/sec.
In an attempt to make this work a while back, I found that although it was possible to send
the proper commands to the hardware to do this, the clocks were found to NOT be out
of phase, therefore simply repeating the same sample on ch B that was captured from ch A.
Looking further into this, it appeared that although everything on the hardware level is
set up properly to do this, the FPGA, which is where the 2 clocks originate from,
was not shifting the B clock, although there appeared to be code written to do this (at least
in the old V2.5 implementation). Looking at the FPGA code, it looks like pin 1, which
receives the command to shift the clocks is not linked to anything. Whether this was done
by mistake, or intentionally because the function did not work well and was disabled
I don’t know.
However, as has been mentioned, this does not increase the bandwidth, only the resolution.
It will prove interesting to see if the new hardware with it’s new FGPA code has changed
The following documents describe how high end DSOs implement their algorithms.
Sin(x)/x Interpolation: An Important Aspect of Proper Oscilloscope Measurements
By Chris Rehorn, Agilent Technologies
Interpolation in Your DSO
Peter J. Pupalaikis, Product Marketing Manager
cdn.teledynelecroy.com/files/whi … 102203.pdf
The essence of what they’re saying is
Linear interpolation performs well when the sample rate is ten times the highest
frequency signal content. SinX interpolation works well the sample rate is at least three
times the highest frequency content
I am too underskilled to implement this. However, these articles might give suitable tips to those better equipped at such work.
And what means: “Two 72MS/s analog channels, Upto 144MS/s if configured to single channel (from .sys
version v1.31)” … if is used only one channel (B is disabled), then it automaticaly using 144MS/ ?
Or it is advertising only ?
I’m afraid such calculations would likely reduce the framerate to an
unacceptably low level on these devices. Don’t think there’s enough
computing power to implement this, it would only benefit the top range
anyways, which is not bad at 7x sampling for a 10Mhz waveform.
Some of the scopes these fellows are referring to cost more than what
I paid for my house… They have much more capable hardware, but then
again, you can’t put them in your shirt pocket.