Looking at the schematic, and being a kind of hardware hacking guy, there are many things that can be achieved with a little soldering…
For example, it seems as though the DSO203 (quad) was designed in such a way that the A/D converter (U6) could be left out and the A/D conversiions done by the CPU. Check the two nets Ai and Bi. Putting the resistors R33 and R34 in circuit rout the A & B channels straight to the CPU (the internal A/D is better resolution, but slower).
The digital channels (C & D) push the FPGA outside its’ comfort zone anyway (bank 3 pins are NOT 5v tolerant but the diode “protection” clamps to 5v - nominally). Poor design choice of components and/or connection to the FPGA.
So… what about simply wiring the appropriate pads of R39 & R40 to the appropriate pads on R33 and R34? Cut the tracks or lift the legs of nets CTr & DTr if you are squeamish about exceeding the FPGA specs, and feed it some analog.
Digital channels still work (unless you cut tracks), and software (CPU, not FPGA) could then give an enhanced 4 channel analog scope up to about 1MHz…