I wonder if there is any hope trying to compile the design with Icarus Verilog (the 0.8 releases) and the tools that come with iceCube 2 but do not require a license (edifparser, sbtplacer, sbrouter). It seems a very thin chance, but it would give us a free (iverilog as in speech, iceCube 2 as in beer) toolchain for compiling designs for the FPGA.
It is very frustrating to have the FPGA just sitting there with the very limited seeedstudio bitfile that doesn’t even trigger properly, when it has the potential to do much much more.