This is the Source and Include folders for APP and SYS, it’s a bit messy!!!
To work fine it require the FPGA2.22, it don’t work with FPGA2.50 or FPGA2.61
@Kannagara
I’m working to it.
SmV1.6-Source.rar (119 KB)
This is the Source and Include folders for APP and SYS, it’s a bit messy!!!
To work fine it require the FPGA2.22, it don’t work with FPGA2.50 or FPGA2.61
@Kannagara
I’m working to it.
SmV1.6-Source.rar (119 KB)
It means i need downgrade FPGA before try your firmware?
I search on this forum, but i cant find FPGA 2.22 version.
In Wiki page You can find all seeedstudio.com/wiki/DSO_Qua … g_Firmware
Attached the full files, I’ve change the filename so you have not to di it to transfer in dso.
To change FPGA, first copy the file .ADR, wait for popup and copy the file .BIN
If You don’t change the FPGA, the SCAN mode don’t work fine.
DSO_Sm_V1.6 Complete.rar (74.8 KB)
I try firmware, while i found 2 bug:
in other, your firmware is cool, and “free source” wich VERY important!
Thank You for your feedback!
When i use 300 simples mode, and set time from 100us to 0.1us, screen refresh 0.5-3 sec.
Yes, I saw the defect, I think also appears on the original formware, I’ll have to investigate!!!
When i use x10 probe and x10 mode, measurment souch Vpp shows right, but diagram on screen not scaled to x10 as on “my big oscilloscope”
The diagram will scaled to x10 when you use a probe with x10 switch in x10 position
Something New in firmware. Yah! right? I have already given up on this device and maker’s programming skills, but here it is; the official 10/26/2011 updates.
Original Links:
SYS_B1.51
APP_B2.52
FPGA_V2.61
BBB
Forgot to Forget and Remember Everything.
SYS_B151.rar (19.9 KB)
APP_B252.rar (30.3 KB)
V261FPGA.rar (22.7 KB)
Example:
CH-A - Used probe in 10x mode (switch on probe set to 10x)
CH-B - Used probe in 1x mode (Probe without switch)
Input on both probe the same. 2 kHz, 0.5V
CH-A in DSO sets on x10, and diagram is not scaled, however Vpp, Max,Min is scaled to rights value.
Maybe, do this:
[if probe sets to x10 mode] -> [V/div on this channel in top menu, replace to V*10] (example 0.1V ->1V… 10V -> 100V )
Otherwise if oscillogram just scaled in *10, then HiVoltage of 100-400V cant be displayed in diagram window.
I see not correct, when CH-A oscillogram shows amplitude 1/2 div(0.1V/2=0.05V), but Vpp shows rights value 0.5V
Thanks for the suggestion, I will try to do it
I’m not a good programmer, I hope that my changes are then enhanced and included in future updates from other experienced users.
Obviously it would be nice if the source was free.
Yes, your position is right, sourcecode must be free!
It will help to develop the project.
Hi, all,
does anybody know settings for the IAR to compile application and system to a definite application storage. E.g. I want to have original Firmware in APP1-2 and the great marcosin’ FW in APP3-4.
marcosin
I have tried your modified software and I am very impressed. I have only one request. Would it be possible to make the “Normal” trigger mode work properly? So when a trigger event occurs, the display is updated and held indefinately until the next trigger event. Thank you for your efforts.
The 1.7 version have :
Ciao Marco, sei Italiano, vero? Anch’io ho difficoltà con l’Inglese, ho installato nel DSO QUAD le versioni che ho trovato qui, poi ho visto che ci stai lavorando tu, ma a questo punto non ci capisco più nulla; ero tentato di installare le versioni che “bbb” ha definito ufficiali, ma a quanto pare il tuo lavoro sembra graditissimo da molti. Puoi gentilmente chiarirmi un po’ la situazione, perché non ci sto capendo più nulla, anche a motivo del mio scarso inglese?
Grazie e complimenti
Michele
Hi, I answered you in mp, but I reply here to shre the information with the others users.
I know that the last official version are APP2.52, SYS1.51 and FPGA 2.61.
Mine is based on official version APP2.51, SYS1.50 and FPGA 2.22.
I have renumbered the versions with my logic always keeping the root base in fact my file is called for example APP25117 denotes APP2.51 with my version 1.7.
On 1.7:
I see, screen refresh on short time interval is much better.
been any improvement in this code?
Hi Marco
about the slow refresh with big timescales, i suggest you to take a look to this page: viewtopic.php?f=22&t=2217
I tried the modified firmware of user Bag2 who fixed this bug in his own release (then fixed also in the Chip’s release, but without sources) and he was so kind to share (at least part of) the source code; if you compare for example his Process.c file with the original one probably you’ll find some usefulf way to fix it also in your code.
(Se non sono stato chiaro magari mi puoi scrivere in PM )
Ciao Marco,
I compiled your source v.1.6 and got a strange result. Wuth no probes connected, I observe the following picture. May be you uploaded some test variant of FW? Could you share the correct one. And v.1.7 if possible.
Thanks in advance,
Vladimir
Hi Vladimir,
I think that You have some problems in optimization options.
For SYS You must use “no optimization”
For APP You must use “High Balanced” or “Size”
You have to downgrade the FPGA to 2.22.
I’ve add the 1.7 source.
Source1.7.rar (135 KB)