That is a great news! I also tried getting a free license with my university informations and now I am able to compile your VHDL code. I am just curious why does it produce only 32kB dat file instead of 64kB as you put in the attachment. When I opened your project it showed some warning message about incorrect settings (invalid device family name and package). I run the synplify tool and then double clicked the “Run all” command. The resulting dat file was about 32kB