Custom FPGA image works!

[jpa]

Today I managed the first time to load a custom FPGA image on the DSO Quad!

This doesn’t do anything useful, it just returns 0x1234 to show that it works. However, if someone is interested you need these:
github.com/downloads/PetteriAim … ALT_02.HEX (AlterBIOS 0.2, install through bootloader)
github.com/downloads/PetteriAim … WN_004.HEX (QuadPawn 0.4, install through bootloader)
github.com/PetteriAimonen/QuadP … x?raw=true (FPGA test program, copy to usb memory)
github.com/PetteriAimonen/QuadP … N?raw=true (custom FPGA image, copy to usb memory)

And for those who want to know how this is done:
svn.kapsi.fi/jpa/dsoquad/fpga-example/ (VHDL source code)
github.com/PetteriAimonen/QuadP … _test.pawn (Test program)
github.com/PetteriAimonen/QuadP … ime/fpga.c (FPGA loader)
github.com/PetteriAimonen/QuadP … e/fpga.inc (QuadPawn library for FPGA)

To compile custom FPGA images, you need a iCEcube2 license. It can be requested here free of charge. I put in my university information and received license with no further questions:
latticesemi.com/products/des … /index.cfm

[gabonator1]

That is a great news! I also tried getting a free license with my university informations and now I am able to compile your VHDL code. I am just curious why does it produce only 32kB dat file instead of 64kB as you put in the attachment. When I opened your project it showed some warning message about incorrect settings (invalid device family name and package). I run the synplify tool and then double clicked the “Run all” command. The resulting dat file was about 32kB

[jpa]

The steps I run:

1. Launch synopsys from icecube2
2. Run synthesis with F8 and wait for it to complete
3. Close synopsys and return to icecube2
4. Run placement and routing

The output file should be FPGAExample/sbt/outputs/bitmap/fpga_top_bitmap.bin and mine is 68088 bytes.

Verify that icecube2 shows these settings:

DeviceFamily iCE65
Device L04
DevicePackage VQ100
DevicePower L

–

Other thoughts:

For some reason timing analysis gives only 40 MHz operation rate for even the simplest circuits. It appears there is some delay involved in the IO pins or something. It runs just fine at 72 MHz though, so it may be some timing analyzer parameters that are wrong.

[JackTheVendicator]

@jpa

DevicePower L

–

Other thoughts:

For some reason timing analysis gives only 40 MHz operation rate for even the simplest circuits. It appears there is some delay involved in the IO pins or something. It runs just fine at 72 MHz though, so it may be some timing analyzer parameters that are wrong.

The FPGA in the DSO Quad is of DevicePower class T (faster than L).

[jpa]

Progress continues. Now I have a functional logic analyzer image for the FPGA.

To try it:
github.com/PetteriAimonen/QuadP … x?raw=true
github.com/PetteriAimonen/QuadP … G?raw=true

To see how it is done:
github.com/PetteriAimonen/QuadP … iccap.pawn
github.com/PetteriAimonen/dso-q … pport/fpga

Results:

Clock: clk  | Frequency: 86.70 MHz  | Target: 71.99 MHz  | 

Device Utilization Summary
    LogicCells                  :       419/3520
    PLBs                        :       167/440
    BRAMs                       :       16/20
    IOs and GBIOs               :       28/72

Works quite well. Pipelining the FIFO so that it operates at 72 MHz was a bit difficult, thanks to ##vhdl on Freenode for help.

The Pawn program is a bit slow for actually capturing anything, the buffer overflows easily. The RLE encoding currently has maximum count of 4096, so it takes quite many samples just to record long intervals. I might have to change it so that if the top bit is set, all 16 bits are used to encode delay.