I am designing a custome cape for a BBG. I want to use the HDMI framer pins, which are also used for SYSBOOT. The pin status are latched on rising edge of the SYS_RESET. Based on power up sequence, the VDD_3V3B rail will be on before this. I am going to use VDD_3V3B to enable my 3V3 DC/DC switcher, which powers all my peripherals on my cape. Since there are pullup/down resistors to my 3V3 rail, these may be advertently pulled to wrong SYSBOOT values at SYSBOOT latchup.
1. Is this a likely failure mode for BBG?
2. I am planning to delay my 3V3 rail until SYS_RESET goes high to prevent this. Is it advisable?
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