Enabling the 3V3 for peripherals for a BBG cape


I am designing a custome cape for a BBG. I want to use the HDMI framer pins, which are also used for SYSBOOT. The pin status are latched on rising edge of the SYS_RESET. Based on power up sequence, the VDD_3V3B rail will be on before this. I am going to use VDD_3V3B to enable my 3V3 DC/DC switcher, which powers all my peripherals on my cape. Since there are pullup/down resistors to my 3V3 rail, these may be advertently pulled to wrong SYSBOOT values at SYSBOOT latchup.

  1. Is this a likely failure mode for BBG?
  2. I am planning to delay my 3V3 rail until SYS_RESET goes high to prevent this. Is it advisable?



Hi Kaushalya

  1. Yes, if the power supply timing sequence is wrong, it will cause the BBG to fail to start.

  2. On Cape, it is best not to connect the pull-down resistors on these pins of Sysboot. If it is to be connected, it must be consistent with the pull-up on BBG. For example, LCD_DATA4 (SYS_BOOT4) is connected to the BBG with a 100K pull-up resistor. Originally high level, it should also be pulled up on Cap. If 10K pull-down resistor is connected to ground, when this pin is powered on, voltage V=3.3V*[10K/(100K+10K)]=0.3 V, it is not high, it will cause the CPU to not start. Even if Delay 3V3, timing errors can’t be avoided because GND is always there.

  3. If you delay the gnd and vccs on the Cap, it may not work, because the power supply may be poured through the IO connected to the Cap.

  4. We have HDMI cape, you can refer to schematic, there is no pull up/down. <LINK_TEXT text=“https://raw.githubusercontent.com/Seeed … _Files.zip”>https://raw.githubusercontent.com/SeeedDocument/BeagleBone_Green_HDMI_Cape/master/res/Schematic_Files.zip</LINK_TEXT>

  5. So you want to connect to HDMI and also connector to other functions? please connect me if i am wrong. thanks.