Any reasons the AR_D12 / FPGA_AR_D12 is treated differently than the other digital io’s that connected to FPGA?
It’s even highlighted on the schematic with magenta rectangle, but there’s no comments around.
All the digital pins has 1K/2K divider, but AR_D12 has weaker 10K/20K, like it’s going into ESP32 ADC, but it’s not.
It’s a FPGA gpio line, similar to AR_D11 or AR_D13.
Is that a mistake?