The product is described as “4 channel” but two of the channels are “digital”.
So in fact there are two channels available for sampling waveforms?
How do the digital channels work, what would they typically be connected to.
Also what is the difference between an “oscilliscope probe” versus a “digital probe”.
The A and B channels have amplifier / attenuatators and connect to analogue to digital converters so they sample the waveform and represent the analogue values captured. So a sine wave looks like a sine-wave.
The C and D channels connect using digital logic levels direct into the sampler which then registers them as either high or low logic levels on each sample point, effectively like a logic analyser. The Quad will treat any level below say 1V as low, and values above 2V as high. One should avoid connecting the C and D inputs to anything other than logic levels like CMOS or TTL.
C and D can be used to capture the timing relationships of logic signals and can also be used as triggers in conjunction with the A and B channels.
Some people also use A and B as quasi digital inputs to get effectively a 4 channel logic analyser.
Analogue probes pass the signal either directly x1 or through a 10x attenuator in the probe. The x10 setting has higher impedance and lower capacitance (typically 10MOhm) to minimise the load on the circuit under test. Digital probes are typically just a simple direct connect as they need to pass the logic level straight through to the input. An analogue probe in x1 mode acts pretty much the same as a digital probe.
Thanks, it all seems quite obvious now 
Are the digital inputs 5V tolerant?
I’m thinking of buying one of these from eBay becuase it means I don’t have to worry about import duty if I use a UK seller. Unfortunately it seems none of the folk reselling these on eBay are including the digital probes 
I wonder why that is.
The C and D inputs each feed through a series resistor (11K) and there is a clamp diode for protection. So they are OK for +5V and reasonably well protected from inadvertent overload or static.
The clamp diode is / was an issue in that the component used had quite a high junction capacitance (~100pF) and this together with the 11K series resistor meant that the bandwidth on the digital channels was limited to about 1MHz and also introduced a relative timing delay with respect to the analog channels. I don’t know if this is still the case with recent production but the v2.7 schematic still shows the original part. Some of us, including me, modded their units by replacing the clamp diode with an equivalent low capacitance device (<1pF) to eliminate this problem. The part I used was a TPD2E009DBZR which I also sourced from an eBay supplier.
Some suppliers include extra probes / some don’t. One can get the mini co-ax connectors (MCX) also on eBay in various forms and I found it useful to get some and make up extra probes anyway.
The inputs are connected (via 11K) direct to the FPGA and parallel with the ESD diode.
The ESD diodes clamp to a nominal 5 volts, but the FPGA inputs are not 5v tolerant.
It is true that these pins are not specifically 5V tolerant like some other pins, and the diode is primarily to protect against ESD. However, the inputs themselves clamp and have an injection current tolerance of +/- 5mA. With 5V input the injected current will be about 200uA. You would need to put about 50V on the input to exceed the spec of the pin and the 11K would also be dissipating 250mW at that point. Obviously it is good to ensure these only connect to normal logic levels to minimise any stress or possibilities for failures.