I found a mention of the possibility of replacing the ADC AD9288BST-100.
Will this change with other chips and/or firmware?
On what features it will have an impact?
In your Wiki you tell about “Upto 144MS/s if configured to single channel from .sys version v1.31”
I do not understand how the original AD9288BST-40 is possible at higher speeds 40MS/s. (see Analog Devices AD9288BST-40 datasheet)
It means original AD9288BST-40 is overclocked?
If AD9288BST-40 is overclocked this working stable on 100% ?
Can to improve the stability is desirable to replace me on the ADC model AD9288BST-100?
Shodan_x, oversampling would not do much since the analog BW is pretty much limited to about 10MHz (and it is not flat either). If the ADCs are pin by pin compatible then the replacement will require good soldering skills and changing the speed of the clock signal, which I assume is generated by the FPGA. Again, without a better analog front end this modification will not improve things much.
DSO in each channel is 72 MHz, the ADC has a mode when the channels are independent and in turn take data from one input. hence the 144 MHz
but it does not work in current versions