Spartan Edge Accelerator - programming the FPGA and serial flash memory using Vivado

Hello, I have been using XILINX Vivado to program the spartan edge accelerator which has an xc7s15 fpga and a on-board W25Q32JVZPIG 3V 32M-BIT Serial Flash memory device directly connected to it.

What is the intended function of this device with respect to the board. Is it possible to use indirect programming to use the JTAG connector to program the flash through the JTAG so that the FPGA device can load the bitstream from the flash (in-circuit serial programming) as described in XILINX document XAPP586 (XILINX XAPP586 application note)

Well, I think others have the question as well, here is a relevant answer.

Short story, the connections are wrongly pinned and will not allow the FPGA to boot from the bitstream in that flash. The shield was designed as a SLAVE board, mostly, with Stand-alone FPGA programming capability. the MCU (ESP32) is used to program as MASTER the FGPA(Spartan Edge Accelerator Board SPI Flash))

It’s incorrect to say it’s “wrongly pinned”, “will not allow”.
There’s no mistakes, it was a design choice. Instead of having two flash chips (one is mandatory for esp32 and must be dedicated to it, the other is optional for fpga), they’ve chosen to omit flash for bitstream.
It saves the costs (maybe not significantly), it adds flexibility by allowing you to reload fpga with different designs on the fly, if the task requires changes in hw.
As a side bonus, it simplifies the relations between esp32 and fpga, you can’t accidentally damage it by having conflicts due to mismatches between currently loaded bitstream, and gpio configurations on esp32 side. The esp32 has full control over the fpga.

Thank you @volodymyr.strakh , from inspection of the schematic of the Spartan Edge Accelerator, if I can ask:

  1. the connectivity between the W25Q device and the FPGA is in parallel to the to W25Q device and ESP32 device - (FPGA_ESP_IO5 == FLASH_SCS, and so on); If the FPGA board is used as a standalone device, is the memory chip able to be interrogated by the FPGA ? Just asking.
  2. what process is used to define a bootloader that implements a bridge between the W25Q device and the FPGA so that the FPGA can read the stored program?
  3. I am using VIVADO/VITIS successfully on this board - while I do have the SEEEDUINO haven’t used it yet as I have good results with JTAG, JTAG-USB and JTAG+UART to download/update programs as you pointed out - it is very flexible and quick. But if I bolted on the SEEEDUINO to download/store and boot/reboot the board, is there a pathway to combine the ELF file generated by VITIS (or perhaps the combined .bin + .elf file to be saved? I guess I am asking how could I get VITIS to generate a downloadable file to be transferred to the SEEEDUINO by flash media, so that the board can then load that executable.
  4. Just curious if the W25Q device could be programmed at all (in an FPGA application, for NVRAM purposes) as it seems the DIO pin is connected as FLASH_SDI/FPGA_ESP_IO8/G14 as is /CS FLASH_SCS/E13, DO/FLASH_SDO/F13 and the clock CLK/FLASH-SCK/G14 directly. I am wondering if this programming can be done without involving the ESP32 MCU.

It would be great to hear directly from the board’s designer, and I’m just a user who bought the board because it’s cheaper than other fpga kits :slight_smile:

While it looks like you could access the fpga, a lot of details is not clear. Is it possible to release (put in high impedance mode) the spi flash lines by esp32, what’s the status of write-protect and hold pins, which is not connected to fpga? etc…
It just might be possible to make flash accessible to fpga as a non-volatile data storage, but it would require a very specific conditions created on esp32 mcu side, it must not map the flash into its code address space, it must not assert write protection, etc. Basically it makes esp32 useless, and that’s not something you would intentionally design.
It’s likely it will be easier to run a simplistic “storage server” on esp32 mcu, and communicate over QSPI interface between esp32 and fpga. No risky conditions, no unclear points, esp32 might perform other service functions - provide access to SD card/WiFi/whatever.