Spartan Edge Accelerator - programming the FPGA and serial flash memory using Vivado

Hello, I have been using XILINX Vivado to program the spartan edge accelerator which has an xc7s15 fpga and a on-board W25Q32JVZPIG 3V 32M-BIT Serial Flash memory device directly connected to it.

What is the intended function of this device with respect to the board. Is it possible to use indirect programming to use the JTAG connector to program the flash through the JTAG so that the FPGA device can load the bitstream from the flash (in-circuit serial programming) as described in XILINX document XAPP586 (XILINX XAPP586 application note)

Well, I think others have the question as well, here is a relevant answer.

Short story, the connections are wrongly pinned and will not allow the FPGA to boot from the bitstream in that flash. The shield was designed as a SLAVE board, mostly, with Stand-alone FPGA programming capability. the MCU (ESP32) is used to program as MASTER the FGPA(Spartan Edge Accelerator Board SPI Flash))

It’s incorrect to say it’s “wrongly pinned”, “will not allow”.
There’s no mistakes, it was a design choice. Instead of having two flash chips (one is mandatory for esp32 and must be dedicated to it, the other is optional for fpga), they’ve chosen to omit flash for bitstream.
It saves the costs (maybe not significantly), it adds flexibility by allowing you to reload fpga with different designs on the fly, if the task requires changes in hw.
As a side bonus, it simplifies the relations between esp32 and fpga, you can’t accidentally damage it by having conflicts due to mismatches between currently loaded bitstream, and gpio configurations on esp32 side. The esp32 has full control over the fpga.