Hello, I am using XILINX Vivado/Vitis 2020.x toolchain to generate FPGA bitstreams and elf application binaries for loading using JTAG connector on Spartand Edge Accelerator. I would like to load them using the Seeeduino board to reduce the need to load the programs/executables every morning when I turn on the computer (the board has no independent indirect memory - all programming is done through ESP32). The XILINX Vivado/Vitis toolchain produces a .bitstream file, and an .elf file, and it is possible to follow the process:
After Vivado generation of bitstream file, prepare hardware definition file (.xsa) and use VITIS to generate the application and a platform. Then in VITIS:
- XILINX > Program FPGA
- (choosing the application to be downloaded) Right click, Run As > Launch on Hardware (Single Application Debug)
In the first part, a download.bit is generated and downloaded using JTAG, In the second part, it seems just the .elf file is downloaded.
What can I do to convert this process to the Suggested Arudino load process ?