Reducing width of Xiao by milling off castellated holes

Products & Technology XIAO
1

Hello, would it be viable to mill off the castellated edges of the Xiao board to reduce the width of the board?

The board is a bit too wide for my application right now.

2

Hi,
Which board, I see some VIA’s under microscope and a Resister next to PMIC (sorta looks like) you could trim back to the Beginning of the Holes? Time to go Frankenstein on one…LOL
HTH
GL :-p

3

The NRF board without the sensors

4

I sanded off the castellated edges and 3/4 of the diameter of the holes on the left side of the board. The board still works.

5

LOL, Nice… :grinning: Getting real small now…
GL :slight_smile:

6

Hi, I did the same with a Xiao esp32c3 with mixed results…

I used sanding paper and removed down to half the hole of the castellated pins on both sides. D1 stopped working but the rest did and I could still make make it work with battery charging and all.

Does anybody know where I can find the PCB model? I could not find it in the SEEED Wiki, all the other Xiao have their PCB drawings but not for the esp32c3.

Cheers,

Sergio

7

Hi there,

Look at the thread “the Best Kept secret from seeed Studio,” I think it is has all of them and the Wiki has a resource tab and there are Board and schematic there as well.

HTH
GL :slight_smile: PJ :v:

3d_c3
3d_c31888×1386 134 KB

8

I am not an expert… but i would say for pretty good account that if you sand down a PCB you ill alays get good results… to a point… obviously physics controls, the smaller you shave down a circular pad, the less the contact area… and the less the contact area the more resistance and the less current capability to the poin that you reach the physical limits of being able to solder to these connection points and to overcome the resistance and to source the current required…. these is just physics… but as to the ability to test it should be successful

if you have any doubt… i refer you to this device

i would assume this device could never work because of the snappable design… that the via could be so small that the board could snap clean… that the via could pass the current and the low resistance to work when not snapped and that the residual ould not short and provide transient losses and shorts and noise… but it functions almost 100%… for hat that is worth