Hi there,
LOL, I wouldn’t want to spoil your fun. You get some more experience , you’ll know Silicon Labs has published several application notes on low-power design and optimizing leakage currents with their EFR32 series.
For example, an application note (or Low Energy Guide) might explain that unused pins should be tied to a known state (by configuring them as outputs or enabling internal pull-ups/pull-downs) to minimize leakage.
I don’t want to spoiler alert you but it’s your parade 
(TSMC my Guy) 40 and 65 mm process, You ever worked in a FAB? I have. LOL and this phenomenon is indeed documented in Silicon Labs’ documentation for the EFR32MG24 (MG24) series. Here are some pointers on where and how this is documented:
In the EFR32MG24 datasheet, there is a section on “Electrical Characteristics” Section 4 , 4.2 in your DATAsheet link or “I/O Characteristics” that specifies leakage current levels for GPIO pins in various configurations (e.g., when configured as an input with no defined level versus when pulled high or low). This section will note that leaving inputs floating can result in higher leakage currents. (as a Technician you know this)… 
and FYI…
The reference manual for the MG24 does also discuss recommended practices for configuring unused I/O to avoid unnecessary power drain. Look for sections that cover GPIO configuration or best practices for low-power designs.
Just look with your eyes at what you posted (3.0v IOVDD) what a dead battery, C’mon man! you see the OTHER numbers in that chart ? The MAX ones? Wouldn’t you saying it’s only 1 or 2 na, be NOT true, could go as High as 250na. just saying… LOL 
it’s your chart.
I get you’re being funny with posing the same form and ? but YOU really should do your own homework first. Just like the life safety certs, they don’t HAVE!
There aren’t “bugs” per se that make Silicon Labs SoCs unusable in low-power designs, but there are several well‐documented challenges and nuances you need to be aware of. They are NOT on a NEON sign anyware, For example:
- Floating Inputs and Leakage Currents:
The datasheets and application notes (for instance, in the EFR32MG series documentation) repeatedly emphasize that unused GPIO pins must be configured (for example, with internal pull-ups or pull-downs or set as outputs) because leaving them floating can lead to higher leakage currents. - DC‑DC Converter Configuration:
Some Silicon Labs SoCs are designed to work with an on‑chip DC‑DC converter to reduce quiescent current in low‑power modes. If the converter isn’t enabled or properly configured, the device may draw significantly more current than expected in sleep modes. Silicon Labs’ low‑energy design guides describe how to configure these regulators properly. - Peripheral Shutdown:
Not disabling unused peripherals (or leaving them in a default state) can lead to higher power consumption. Documentation and application notes recommend explicitly shutting down or reconfiguring peripherals that aren’t needed during deep sleep. - Errata and Silicon Revision Nuances:
Like all semiconductor products, early silicon revisions of Silicon Labs SoCs sometimes have errata that affect power consumption. These issues are documented in the “Errata” documents available from Silicon Labs. Have you ever looked at one? I’m betting NO, and you probably don’t know where to look either. “Users are advised to check the latest errata for their specific SoC revision to ensure that any known issues are accounted for in their design”. E101 - Board-Level Design Considerations:
Sometimes the additional current draw isn’t just from the SoC itself but from supporting components on the board (such as voltage regulators, decoupling, etc. just ask seeed ).
Ok, NOW! You have my rhetorical answer. 
the horse is dead.
GL 
PJ 
Now let’s see how long they take to fix reading the battery voltage.Tick/Tock 
