I have a project that is max’d out for gpio, so I’m reusing the JTAG pins as inputs. I’ve disabled JTAG with
and initialised the pins as inputs with internal pull-up resistors. Everything is working fine for PB3, PA13 and PA15, but PA14 is stuck low, as if the internal pull down resistor is enabled instead of the pull-up. PA14 is the the JTAG clock by default and is the only JTAG line that uses pull-down instead of pull-up (section 7.3.1 of the processor user manual). I’m wondering if the hardware for that pin is less configurable than for the standard GPIOs? Anyone else run into this? I figure I’ll do some testing to see if I can add an external pull up, and if that doesn’t work maybe swap it with another pin and use it as an output. Both options are a little bit messy, so if there’s a software fix that would be better!
Thanks for any thoughts,