Hello, I purchased, and got running the Spartan Edge Accelerator board (very high engineering quality and design features). I have never programmed with JTAG before, only through serial i/o into flash on various MCU. I am a hobbyist in FPGA stuff.
The device shows in Windows 10, as a “Xilinx USB Cable”. It does power on. I have used the 1x7 SIP connector to connect 5 (five) flying connections to the target board: TDI – TDI | TDO – TDO | TCK-TCK | TMS-TMS.
But I have a question:
On the Spartan Board, there are few pins listed in the schematic on FPGA_Download-Interface(2), which are: VCC_3V3, GND, FPGA_TMS, FPGA_TCK, FPGA_TDO, FPGA_TDI. The interface is shown in first page of schematic.
I do not want to damage the FPGA in my first attempt to program it. I have powered the target board with an USB3 Type C connection to my laptop. I see the programmer Status LED is green and the programmer seems to be recognize.
Should I connect the 3V3 line to the RED pig tail cable from the DLC9LP?
Separately: What could be the role of the JTAG Mode/Slave Serial Mode switch SW4 (first page of schematic) in relation to this programmer? Is that for debug applications mode?
For extra information at the present, I loaded up the sample/tutorial FPGA file and went throught the build stages of spartan edge accelerator board io example and in particular the section entitled Standalone Mode. What am I doing wrong to locate the target board which is connected (a) via USB3 cable and powered on (b) the five pig-tail cables mentioned above.
What should the status of SW4 (JTAG/Serial Slave) be for programming? What should the status of the Top Left power switch be for programming?
Thank you.
I am using XILINX Vivado to try to “find the target”
I’m currently messing around with the JTAG interface on the Edge board as well.
From my understanding and testing, you switch the last DIP switch into JTAG mode (no connect) (pin 5 on the dip) and the jtag interface should be ready to go.
I’m stuck trying to program mine, because I realized that my DIP switch doesn’t seem to be working, it doesn’t actually remove connectivity between the pins when I switch it to JTAG mode. Somehow, it’s only the last switch, all the others seem fine. If you still run into problems, that might be your cause as well, I just tested it by touching both sides with a multimeter, and got 0V when switched to SLAVE, and 0.14V when switched to JTAG, while the others show 3.3V when switched off.
Top left power switch shouldn’t have any effect as long as the Edge board is getting power and lighting up the green LED.
Sometimes the JTAG cables want VREF connected so that the JTAG adapter knows that it is connected to a device, so feel free to connect 3V3 to the VREF pin on the cable, the adapter shouldn’t be supplying voltage, it just reads the voltage on the reference pin.
Wow, I just succeeded. Thanks for the encouraging note. Wish I had seen your reply sooner - spent the most of the week moping around and pulled the trigger to buy the Seeduino board from SEEED website just moments ago, before checking the forum. I wanted to have a way to program it in case (per a friend) I had purchased a no-good JTAG programmer.
Result
My console output is below. I used the new SEA board connected to a Generic (Chinese) XILINX compatible Platform Cable USB, connected via USB2. The pinouts connected to the FPGA board were VREF, GND, TMS, TCK, TDO, TDI. The DIP switches (all 5) were left as-is, in the OFF position (JTAG label). The board was powered with a USB3 cable in a USB3 port. I used a Anti-static wrist strap as the board is pretty barebones at the moment and I had to put it on a anti-static bag for protection. I followed Chapter 4 of Vivado Design Suite User Guide Programming and Debugging UG908 (V2019.2) October 30, 2019.
The Green LED XILINX FPGA Programming Adapter - Amazon source popped up when the hardware target was identified. I think I connected the programming adapter first to the computer, and then the USB3 to the SEA board. During the discovery process, the USB interfaces disconnected, reconnected several times.
here is the output from VIvado IDE 2019
connect_hw_server: Time (s): cpu = 00:00:04 ; elapsed = 00:00:25 . Memory (MB): peak = 754.469 ; gain = 11.590
open_hw_target
INFO: [Labtoolstcl 44-466] Opening hw_target localhost:3121/xilinx_tcf/Xilinx/00000000000000
open_hw_target: Time (s): cpu = 00:00:07 ; elapsed = 00:00:08 . Memory (MB): peak = 1987.602 ; gain = 1233.133
set_property PROGRAM.FILE {C:/Users/Eva/xilinx projects/SEEED1/SEEED1.runs/impl_1/test.bit} [get_hw_devices xc7s15_0]
current_hw_device [get_hw_devices xc7s15_0]
refresh_hw_device -update_hw_probes false [lindex [get_hw_devices xc7s15_0] 0]
INFO: [Labtools 27-1435] Device xc7s15 (JTAG device index = 0) is not programmed (DONE status = 0).
get_property REGISTER.IR.BIT5_DONE [lindex [get_hw_devices] 0]
0
open_hw_target
INFO: [Labtoolstcl 44-466] Opening hw_target localhost:3121/xilinx_tcf/Xilinx/00000000000000
set_property PROBES.FILE {} [get_hw_devices xc7s15_0]
set_property FULL_PROBES.FILE {} [get_hw_devices xc7s15_0]
set_property PROGRAM.FILE {C:/Users/Eva/xilinx projects/SEEED1/SEEED1.runs/impl_1/test.bit} [get_hw_devices xc7s15_0]
program_hw_devices [get_hw_devices xc7s15_0]
INFO: [Labtools 27-3164] End of startup status: HIGH
refresh_hw_device [lindex [get_hw_devices xc7s15_0] 0]
INFO: [Labtools 27-1434] Device xc7s15 (JTAG device index = 0) is programmed with a design that has no supported debug core(s) in it.
hey, just tested the onboard FPGA program functionality. Could I ask if this is the expected behavior?
The FPGA device when programmed, enables FPGA_DONE led. At this time, we can interact with the program A XOR B or something like that: SW1 (L1 led on), SW2 (L1 led on), SW1 and SW2 (L1 led off), etc.
When I reset the FPGA (FPGA_RST) what is supposed to happen? Will the bitstream program be persistent between reset cycles?
Does this FPGA device have onboard flash and are we writing (the bitstream) to that flash code, or is it that we have to (using FPGA programmer, or ESP32) load the bitstream each and every time after power on.
