DSO Quad Redesign

Not sure if this belongs here so moderator please move if it would better fit somewhere else.

So being the tinkerer and dreamer that I am, I was looking for a system schematic for an Oscilloscope online partially because I wanted to understand how they work. I stumbled upon the DSO Quad (Quad) and was surprised that it was open source and based on an ARM microcontroller. I started delving into the specs and found that it would be adequate for my needs. I ended up picking a Quad up on ebay and downloaded the schematic as well.

While looking over the schematic, I started thinking to myself, “Wouldn’t it be nice to have a pocket oscilloscope with a bandwidth of 100+ MHz and a sampling frequency of 200+ MS/s ?” This started me out on the process of redesigning the Quad to these specs.

Attached are the components for which I have spec’ed out for the redesign. Unfortunately I couldn’t stay with a microcontroller and had to switch to an applications processor, but the switch did allow for the removal of the FPGA because the maximum core frequency of the processor is 1GHz (though this might be added back to obtain some additional functionality.) Additionally I have begun to look into the implementation of making the Quad a Multi Signal Oscilloscope (MSO) with both a logic analyzer and logic word generator multiplexed together. I am thinking it would be easier to instead of developing an entirely new firmware for the processor, it might be better to use either Linux or Android as an operating system and developing an application for the operating system (you will see why this could be supported when you view the parts list.)

Tell me what you think.
Parts List.xlsx (12.2 KB)

I’m not sure if I’m thinking correctly, but, to achieve a true analog BW of 100MHz, you need to sample at least 8x100MHz. So, the 250Msps ADC might be a bottleneck. I know 200Msps is sufficient to fulfill the Nyquist criterion. But to see a decent wave, 8x is minimum.

Please enlighten me if I’m wrong.

I was just reading the Quad Bandwidth thread and agree. Let me see if I can’t find something. Only issue I see though is whether there will be sufficient clock cycles to display the data and to perform other functions. Not being a programmer, I can’t accurately account for issues related to firmware, I can guess but that guess could be wildly off.

Edit: 11/1/2013 11:04 AM GMT
Found three ADC’s that might be better. See the revised parts list.
Parts List.xlsx (12.3 KB)

That is quite enough to close the topic

What I meant by this was I don’t like to program, not that I can’t. I am quite capable of writing and reading/understanding code, specifically C/C++, but do to past experiences have not felt the need to get into. I can write code but it is crude and probably takes more lines than what may be necessary but it gets the job done.

How does your comment help me and others refine my redesign of the DSO Quad? Not being a programmer should not exclude this discussion nor warrant the closing of this thread. If this thead is better located someplace else than a moderator can move it there. That is all I have to say on that.

On a seperate note:

In the parts list, replace the ADC part number ADC12D500RF with ADC12D1000. I selected the 500RF based on a super quick search on parametric table versus reviewing the datasheet. I discovered 1 GS/s is only possible when the two ports are interleaved. The D1000 is a straight dual port 1 GS/s ADC.

If so, as the first approach it’s better to achive 72MHz aquisition @ one channel. It will not require any hardware mod as everything will be done in SW.
I do not trust you or somebody will be able to resolder DSO board successfuly.

Just looked @ your Partlist. Are you serious?
Do you mean to make new PCB for the DSO?
Or you think you could replace existing parts with the new ones?
Both ways are crazy.
You can simply start a new project, say on Kickstarter :laughing:


I discovered some interesting information that may be applicable to various intiatives. Earlier you said,

To which I responded,

Your statement is true if you are looking for a connect the dots methodology. I now think a slower ADC would work as well. Check out this article on EE Times. However, I do not know how this would work for any signal other than a periodic signal. My digital signal processing (DSP) knowledge is a little rusty.

The article explains how even Agilent’s 1GHz BW oscilloscopes just meet the Nyquist criterion with a sample rate of 2.5x the bandwidth but still show smooth waveforms using interpolation. It goes on to state that while using interpolation, there is virtually no difference between a reconstructed signal sampled at 25x the bandwidth, with and without interpolation, and a reconstructed signal sampled at 2.5x the bandwidth, with interpolation. The Application Note From Agilent, located here, says much the same thing.

Interesting articles. Thank you. I learned something from that.