The block is meant to only work at 72 MHz. This is because I want to use the memory bus synchronously (it’s easier to design and to debug). This means that because the CPU always runs its memory bus at 72 MHz, the FPGA also has to run at 72 MHz. Because of the RLE coding, the samplerate should not be that important - but it could still be divided on the FPGA side if necessary.
The VHDL code is here, btw:
<LINK_TEXT text=“https://github.com/PetteriAimonen/dso-q … pport/fpga”>dso-quad-logic/fpga at fpga_support · PetteriAimonen/dso-quad-logic · GitHub</LINK_TEXT>