DSO Quad Logic analyzer application


Here is a (preliminary) version of my Logic analyzer for the DSO Quad:


It has the following features:

  • Easy scrolling and zooming
    20 kB capture buffer (10 - 20 thousand transitions, time unlimited)
    Automatic grid
    Collapsing of long idle periods
    Saving to VCD and BMP
    4 channels, 500kHz samplerate
  • [/list]

    I wish I could synthetize some code for the FPGA, it would make it so easy to achieve 72 MHz samplerate.

    Even though the quad has a lot of issues, this is one of the reasons I like the DSO quad. You can hack it yourself. I still have to get started though :wink:

    Indeed. I think this is what makes DSO Quad unique :slight_smile: Even though there has been some homebrew popping up for Rigol, too, it’s not an open platform like the Quad.

    Cool, this looks very good!!!

    The zooming and scrolling works excellent, fast and smooth. I like it a lot already.

    Some cursors that snaps to transitions and basic time-calculations as well as a horizontal time-scale would be nice.



    Very, very nice! You said it is limited to 500KHz? Perhaps Seed can help you get the tools for 72Mhz?

    Thank you so much!

    Great! Nice to see that somebody is still working on the DSO Quad.

    I agree with Johan, the thing I miss most are the timescale display and some cursors.


    Two questions to the author:

    How can I download the source code using Windows (without having to download each file separately)

    Regarding your superb frequency response analyser: i’m trying to extend the range up to 2MHz, and I try to use the “set_square_frequency” function for generating frequences above 200kHz. But the DSO crashes (hangs) when I call this function. The ___Set (DIGTAL…) calls are the cause, even with good parameters, but I have no idea why!


    Yeah, time measurements would be a great addition and not that difficult to add. I’ll have to do that sometime. I have plenty of plans how to enhance this, but thought I would release something in the meantime :slight_smile:

    You can use e.g. http://tortoisesvn.net/downloads.html to download the code on Windows.

    Re: the frequency response app, the measure_rms function waits on the DMA to get the phase correct. See rms_measurement.c line 35-37. If you don’t care for the phase measurement, you can comment that out. Otherwise you’ll have to wait on the timer instead.

    Graah :evil:

    Just spotted the Ai and Bi lines in the schematic - direct lines from analog inputs to the STM32 - an answer to my prayers!

    Spent two hours trying to get them to work, then realized that the resistors R33 and R34 are not actually on the PCB, even though marked in the schematic.

    what a mess

    I have installed your application to my DSO Quad (HW 2.60, Sys_151, App_252, FPGA261) and all I can see after turning DSO on (with third button pressed) is splashcreen with last line of text “Logic Analyzer © 2012 jpa”. Then it just seems to be stuck here. It does not react to any buttons or signals, I just can’t get anything else than splashcreen. Is it a known bug? Or am I doing something wrong?

    Thanks for any advice and for your great (from what I have seen and read on your pages) software.

    Hmm, interesting. It is probably something about your hardware that is different from mine. When did you buy your DSO Quad?

    You can try holding down button 4 for about 10 seconds. After that, wait a few seconds more and reboot the device and check if there is a file called memory.dmp.

    If the application is not completely stuck, holding down button 4 initiates a memory dump. It should also show a message on the screen, but if my LCD code is busted it won’t.

    I ordered my unit sometime around 5/5/11. I had no time or opportunity to actually use it - until now. I updated software (sys, app, fpga) yesterday - following Quad wiki and went up to the latest official versions - everything seems working perfect. Today I decided to try your logic analyzer. I have now tried holding button 4 according to your instructions - nothing happened, no message and no memory.dmp after rebooting to App1 and connecting to PC as USB drive.

    One (maybe) interesting thing - when booting to your App3, there appears to be tiny display artifact - something what seems like 1 red pixel (looks like dead pixel on some unperfect LCD screens). This red dot is located at the very bottom line and horizontally it is located somewhere below most right pixel of character ‘a’ in “…2012 jpa”. When I keep holding button 3 there is no red dot, but ~0.5s after releasing it it shows. I can provide photos if needed.

    Please try this application (it installs as APP3):


    You should get a display something like the following:

    Yes, I can see 100% perfect copy of your image when running attached test app on my device. Everything is same, numbers, text strings, color stripes…

    Then I again flashed your Logic Analyzer app - still the same, stuck at this:

    And by the way - thank you very much for your time, I really do appreciate that you are trying to help me.

    I have the same problem, I can see the first screen only. The test app runs fine.

    added: no red dot

    Red dot is not shown after every attempt. It is quite random and I haven’t found out what it depends on.

    Please try this one. It displays some status information on the bottom row of the screen so that I can see where it hangs:


    BTW. Thanks for helping trace this bug down. It’s a bit difficult when it doesn’t occur on my device :slight_smile:

    011 Enabling capture TIM1 priority

    Hmm, very interesting!

    New test app at the same url, please try:


    Same screen as before (011 Enabling capture TIM1 priority)

    Out of curiosity, are you using same version of SYS, FPGA… as me?