Here is a (preliminary) version of my Logic analyzer for the DSO Quad:
It has the following features:
20 kB capture buffer (10 - 20 thousand transitions, time unlimited)
Collapsing of long idle periods
Saving to VCD and BMP
4 channels, 500kHz samplerate
I wish I could synthetize some code for the FPGA, it would make it so easy to achieve 72 MHz samplerate.