Yeah, that is correct. The way the signal capture is implemented now is a very big hack, because at the time the FPGA tools were not available.
My real plan is to implement the capture on the FPGA side.
In fact, I already have a FPGA image capable of doing this, and also a test program:
<LINK_TEXT text=“https://github.com/PetteriAimonen/QuadP … /LOGIC.FPG”>QuadPawn/Programs/LOGIC.FPG at master · PetteriAimonen/QuadPawn · GitHub</LINK_TEXT>
<LINK_TEXT text=“https://github.com/PetteriAimonen/QuadP … iccap.pawn”>QuadPawn/Programs/logiccap.pawn at master · PetteriAimonen/QuadPawn · GitHub</LINK_TEXT>
It should be pretty simple to integrate it. Just need to copy over some of the FPGA access code from QuadPawn and replace the signal capture part in the logic analyzer (it’s currently in main.cc). It should allow overflow-free capture up to the 4096 sample FIFO, including RLE encoding.
So why haven’t I integrated it yet? Two reasons: no time, and I have something even better in the works. The FPGA should be able to also further compress the data, which would increase the capacity and speed up display drawing. However, it is difficult… 
If you can help with integrating the current version of FPGA capture, it would be very useful.