DSO Quad Logic analyzer application

Upon reading the “oh noes” at the top, it looks like the ADC FIFO can’t be read fast enough, which would make sense since the signal was so fast. Would a better approach be to send a warning message to the user “Warning: ADC FIFO has overflowed. Output may not be accurate”, rather than forcing a restart?



If this was your plan but you haven’t had time to implement it, I might be willing to help you out with that. I have a bit of experience with TI’s LM4F series of M4 chips, so I ought to be able to help out some with an M3.