DSO NANO - how we users can impact next hardware design !!!

Hi Shazan,

i’ll try to explain to you although i have only a couple of minutes right now.

When circuit is USB powered, no problem at all.

If circuit is battery powered, as there is some current consumption, there will be a voltage drop across transistor. Supposing transistor has 100 mOhm and circuit draws 200 mA => 200mV. If battery is only a bit discharged (say 3.5V) then the regulator (3.0V) is operating in its limits of regulation (not really, but near).

The SD card isn’t the problem here (many of them work in the 2.7V-3.6V range) nor the Cortex (2V-3.6V) but the ADC reference. ADC uses VDDA to reference the VREF+ so if battery voltage drops say 3.3V (as the current in the VDDA branch is lower), we are losing accuracy in the DSO readings.

Of course, i consider this a trade off and otherwise the circuit looks very good to me.


Note1: i agree that the SP3232 trick is a neat one, but the output regulation is far from ideal (no linear regulator inside, it uses a discontinous mode with a 5.5V treshold).


E=I*R, therefore: 0.200 Amps * 0.100 Ohms= 0.020 Volts. The Fairchild data sheet shows that with a gate voltage of -3.5 V the Rds is 0.100 Ohms.



you are absolutely right. I unfortunately shift the units.



I started to draw the schematic in EAGLE format. I have modified a little your original schematic because i thought R21 (1Ohm) and the 10K resistor are not needed. Maybe should we keep R21 for current limiting purposes in the switching process, but i think thats not an issue.

Circuit diagram is in the image below. It’s also necessary to reduce the charging current a little in order to reserve some of the USB current to power the DSO Nano.

The MCP73831 has a pin to indicate if battery charging is complete. So maybe it can be used to report charging status in screen (only one digital pin needed).

Battery - EAGLE 5.7.zip (29.7 KB)

Hi Slimfish,

Your schematic looks good.

R21 was added by Seeedstudio in Rev 1.3 of the PCB. It looks like a current limiting device, but its real function is a fuse. Since there is no charging IC, if the battery & diode shorts, the power dissipation in the 1 Ohm resistor is nearly 100 x the rating of this 402 device, so it will open.

You are right, this resistor is not necessary with a functioning charge control IC.

The 10 K resistor I added is not necessary, since R25 and R26 will discharge C16 and turn on the FET.

I never looked at the charge current with the IC. Since you brought it up, and other postings have mentioned issues charging from USB ports, the charging current is way too high. Since we don’t have access to the battery manufacturer’s specifications, and the circuit does not have thermal sensing of the battery, fast charging at 1x the battery Capacity © is another way to shorten the life of the battery.

Normally the standard charge rate for these batteries is C/10, which in this case would be 0.5 Ah/10= 50 mA per hour. This means a fully discharged battery would take 10 hours to charge. Without more information about the battery, I suggest a compromise of 100 mA charge current, yielding a full charge in 5 hours. This would require R27 = 10,000 (10k) Ohms.

Connecting the “charge state” pin to the uC should be straight-forward. The IC has a version with a 3 state output indicating “charging” and “charging finished” (MCP73831, same cost).

There are excellent Battery & Power Management ICs from many vendors which could be used, but they cost significantly more (>2-5x).

NOTE to all in this post: two of the outstanding features of the DSO Nano which attracted me are the price and size. While firmware features and PCB traces have no production costs, hardware parts do. If portable full featured, 2 channel DS scope is what you want, they are available for $500 - $600 (i.e. Hantek and Owon). Many of the choices made by SeeedStudio is this design were obviously made with getting the most performance for the least price. So while we can suggest improvements, try to keep in mind these factors.



as i bought DSO a few months ago maybe the capacity has increased but the battery my DSO has is 680 mA (at least in the markings). Although standard charging rate is safer for the batteries, i think something slightly greater than the standard charging rate can be used (say C/4 or C/3). Charging it in three or four hours seems a good battery life/usability constraint.

I agree with you in the fact that DSO is attractive because is small and cheap. But i also think that hardware can be enhanced for a few (<5) bucks more. And that’s where the funny game starts.

I also think that this circuit in particular can`t be improved much more. So maybe it’s time for others to comment on it (if they found any flaw) and to proceed with other DSO blocks.

My next proposals:
-Power management (simple). If you forget the switch on -> battery dead. This is a mix of hardware and software, but if there is no hardware to support it, software will never “use” it.
-Dual channel input (complex). Duplicating the hardware is the obvious solution. I want to make a better aproximation. This point could try to address
*Variable input impedance of actual stage (1 MOhm is only in the manual)
*AD+DC measurements. Actually the harware support some kind of AC measurement (thanks to PWM feedback) but as far as i know, it has been never implemented in software.
*Automatic calibration
-Signal output (medium)

Enough for today. By the way Seeedstudio… it will be very interesting to have some feedback from you!!!

Thank you very much,


Thanks Shazam and Slimfish, I’m a bit dazzled about your conversation. Seeed didn’t design the circuits, you may see from the box that it’s the work of Mr. Cai Xiaoguang (aka Bure if you read the source code), a very veteran electrical engineer and luckily our closest partner. We are more apprentices in this product, I’m consolidating all available resources from inside and outside Seeed Studio to make DSO nano better.

I’m keeping consolidating the ideas from forum, blog ,email or anywhere I can see them. We will add the charging circuit in next revision soon, along with other improvements <5$ for current version. I will generate a list of fix/improvement/TBD soon.

For SP3232, we will modify it in the next version with TC1240.

Thank you so much for the suggestions! I will get back to you soon.


I am working on a better input amplifier already. It is busy where I work, so it may take several nights. My goal is to also eliminate the '4051 switch. I am also thinking about equalization for the X1 and X10 probes.

If you are thinking of using the TC1240, I suggest looking at the TI TPS60403, which is almost 1/2 the cost.

This function (power supply for the input amplifier) should be chosen to match the requirements circuits (ICs) of the input amplifier.

I will keep you updated with what I find for a better input amplifier circuit soon.


Hi all,

in my last message, i proposed a few DSO areas that could be improved. As i think input stage was the most difficult (and interesting one) of the list, i started with that.

My basic design goals:
-Cheap enough (<$5)
-Input impedance 1 MOhm for the whole input range (x10 probe friendly)
-AC+DC capable
-More accurate & less noisy
-Easy to calibrate (Offset + gain)

Other less important goals:
-Small size
-Single supply (while conserving ground for reference)
-Easily extendable to dual channel

The image below shows the designed circuit. As depicted is dual-channel, but can be easily ported to single channel. The integrated circuits used don’t have to be those exactly. Input stage AD8615 (single op-amp) can be replaced by a cheaper dual op-amp version (AD8616) or by less capable version (like AD8602). Both op-amps are from Analog Devices, but any other that fits input noise, input current, Vos & GBW parameters can also be valid.

For the programmable gain amplifier a LTC6912 is used. It’s digitally controllable, dual channel, low noise and has an integrated midsupply. Other alternatives exist and can also be used with minor modifications/additions (MAX9939, PGA113, AD8231…).

In terms of cost, TL082, SP3232, HC51 are not needed anymore so althought initial IC cost is near the $5 for the dual channel version, the final cost will be lower.

As i said in a previous message, this schematic is only a schematic (a very first draft of it). Althought i made some minor simulation of it, it’s necessary to build it to check if everything works as expected. I expect to build it in a few days to validate it. In the meantime, all comments/suggestions/complaints are welcome.


Hi Slimfish and all,

I have finally had some time to spend on the Programmable Gain Input stage. Slimfish, the PGA ICs you list and the LTC you feature in the schematic all have different characteristics. The LTC6912 has poor input characteristics (low impedance) so it requires the two op amp buffers you added. Another issue is there is No way to adjust the offset on a large scale. This is likely used to adjust the vertical position of the trace by the U10 pin PB11 ST uC.

After having evaluated the parts you list and many more, the TI PGA113 will provide the High Input Impedance, Low Capacitance, Low Offset & Drift, Self Calibration, and a Reference Input which can be used to move the trace vertically. It also has two separate power supply pins, one for the amplifier and one for the output buffer to match the ADC in the ST uC. The PGA113 has a two channel multiplexer, a high constant impedance and the bandwidth, noise, distortion and drift are more than adequate for the DSO Nano.

It runs off the existing +5 and +3 V power supplies (does not require an +/- supply) and does not need a separate input buffer. So this eliminates the U4, U5, and U7 ICs. Note that U7 also is the output buffer for the test signal (U10 pin PD 12), so a small buffer op amp will be needed.

To use this part, close attention will be needed to properly de-couple the power supplies, filter the PWM out from U10 pin PB11 for a clean DC offset voltage (may also require a Buffer Op Amp), and layout and shielding to minimize noise. The inputs should have a 10,000 Ohm or higher resistor in series to limit overload. A 100 kOhm HV resistor would be better (protects to 1000V input) but it may affect the max bandwidth a bit.

The part is less than $2.00 (about $1.00 in a full reel quantity).

Another possibility is to use the TI PGA117, which has 10 multiplexed inputs. This would add the ability to use it as a 2 channel analog input with an additional 8 channels of logic. Unfortunately this would require something like a 10 pin 1 mm header and a cut out in the case to access the connector for the 8 Logic Inputs. I suspect that the uC would require additional memory (external) as well. Just a thought.

Auto Power Off and DC Input. I think most people would not want a simple Auto Power Off, unless it could be adjusted for time and disabled. This may cost more than it is worth. With a good charging circuit, battery life should be good, and when connected to external USB power, it is not an issue. Small USB power supplies are readily available for a few dollars on e-bay and elsewhere. DC input would be difficult to implement, especially with some Overload Protection for the DSO Nano.


Hi Shazam,

i’m very glad to receive some feedback from you. Although i want to comment some of the points you addressed, i would like to start with a short explanation of how the circuit i posted works.

The most important concern for me was the 1MOhm input range. So everything is built arround this. The input stage is done with IC1, which is configured as an inverting amplifier with a gain of G=1/30. This way, all DSO range (±40V) is supported without modifying the input impedance. Obviously there are many other solutions, but they generally involve the use of manual switches, reles or solid state switches (optocoupled or similar). None of them are suitable here (size, cost, current consumption). Main disadvantege is the small signals are also divided by 30.

Capacitors C5 & C7 are needed to propagate fast signals. Input impedance is so high that even the OA input capacitance would act as a low pass filter. They conform a capacitive divider which propagates fast signals and have to be properly matched with the resistive divider and hence the 647pF (non standard value) value on C5. Whitout these capacities input stage simply won’t work for “high frequencies”. The advantages over the original circuit are mainly two: there is only a capacitor to tune (C5) and input impedance is 1Mohm for the whole input range.

What is it important for the AO at this point? I considered these factors: offset (static + drift), input current, CMRR, noise (V, I) and GBP (Gain Bandwidth Product) and supply range. Doing some math with the AD8601 values (big numbers - refered to DSO INPUT):
CH_A offset (due to input current): 0.2 pA * 1 MOhm = 0.2 uV
CH_A offset (due to input offset): 80 uV * (967K/33K) = 2.42 mV

There are a couple of components not yet explained in the input stage: IC2 & C1. These two conform the AC/DC input selection. The idea is to have C1 shorted for the DC measurements and open for AC. I think is important to have an AC measurement mode, useful when you have to measure the ripple of a signal, a small signal with a big DC offset, etc. In the original circuit this was done by modifiying non-inverting input in IC5 amplifier with a filtered PWM signal.

The presented circuit won’t work. Inverting input is not referenced to any point and the input current will charge C1 either to VCC or GND in case of an AC measurement. And the leakage of IC2 is orders of magnitude greater than IC1 input current, so this is a big no-no. In order to have a working circuit, this capacitor has to be connected between IC1 output and the input of the LTC.

After the input stage comes the amplifier. The input signal has been divided and offseted (also inverted) by IC1 to modify its range to 0…3 V for a -40…40 V input. Now it’s time to amplify it a little in order to sample it. At this point, input impedance of the second amplifier has no importance as it’s sourced by IC1. The important factors now are offset, input noise, GBP and gains.

First of all, the LTC. I’ve also considered the PGA113. I have worked with it in a couple of designs and performs very good for the price. But i partially discarded it for a couple of reasons. Offset, drift, noise and multiplexer are better than fine, but GWP is only 8MHz. That means 3dB attenuation @ 380 kHz (page 5 of datasheet) with a 10 kOhm load and G=100. And that is a lot of attenuation. It’s true that G=100 would be the 10 mV/div scale, but it is something to account for. Also, VREF input is not a high impedance one so an extra opamp is required to set bias level. In contrast, LTC6912 has 33MHz GWP and with an integrated midsupply (VREF). Obviously, the input impedance is lower, but that is not a point here as the first amplifier is needed in any case. And for the other input characteristics, noise is similar and Vos is higher for the LTC but small enough (125 uV typ.) to not be a concern.

The offset adjust you mention initially puzzled me. The original scope doesn’t have an AC measurement mode, so modifying reference to have a pseudo AC mode is a good aproximation… but better than an AC mode itself? I don’t think so. In any case, its easy to modify the non-inverting input of the first amplifier to do that (as the original scope do). Using Vref in PGA113 for the same function it’s not possible unless you have an input buffer to convert the DSO input range to 0…3 V.

If you plan to make PGA inputs the DSO input with a 10K resistor then two problems arise: input impedance is undefined and PGA inputs will function well within supply ranges but input clamp diodes will do its work beyond 0…VCC. If the resistor is 100K then another one is added: input current is 1.5 nA, so input offset will be displaced 0,15 mV. It’s very likely that i don’t get the whole picture well, so please clarify connections.

Two channel analog input its worth when the two channels are sampled at the same time. Although PGA117 switches very fast (200 ns), it must be commanded to do so, which takes enough time itself to hinder its use in higher (100 ksps) sampling rates. And AFAIK the uC has to ADCs.

I don’t really know what people want. But if i forget the DSO switch on and the battery gets depleted (3 hour) resulting in a dead battery, then i will be certainly upset. Leaving apart that a single “usual” mistake has costed me 10+ Bucks & 15 days (delivery).


Thank you so much for the designs!
As for the manufacturing part, I have done the sourcing a bit, seems mouser and digikey don’t have much stock of either PGA113 or LTC6912. Not sure if it is temporary long term shortage, but the lead time might be too long for practical manufacturing. I will be checking both from local market and propose to Mr. Bure to integrate into future design.


in the picture below i draw what could be the input stage schematic with the PGA113. This time is draw in protel as i use it more frequently than EAGLE.

Please note that despite my comments to shazam, both circuits are substantially better than the original in many ways (constant input impedance, AD/DC modes, precision, size…) and both are designed to be simple to calibrate and to control. The drawback is that both are more expensive than the original one. Maybe the PGA113 is even cheaper as it replaced a lot of circuits (U7, U4, U5) and components.

I hope the integration into a future design could be done as soon as possible, as i’m looking forward to get a dual channel DSO Nano.

Note: there is another input configuration possible in which one of the PGA113 inputs measure AC signal and the other measures only DC component of the signal (low pass filter). This way we have both precision in AC and in DC.

Note2: if PGA113 is difficult to get, you can try with PGA112 (binary gains instead of scope ones -see datasheet-)

Hi Slimfish and ESP,

Nice detailed post! My comments:

The DSONANO is not a laboratory instrument with high bandwidth. If the sampling rate is 1 Msps then the max usable input is <500kHz. The internal ADC in the ST uC (or any ADC) generally cannot resolve the number of bits claimed. The ENOB with noise factored in the calculations, and by empirical measurement, is lower by 2 or more bits (i.e. 14 bit -> 12 bit, 16 bit ->14 bit, etc.) of reliable measurement. This impacts not only the S/N but the resolution out of a maximum 3 volts. The resolution determines the offset which can cause an error in the signal measured. Essentially, the offset numbers you calculated are much, much smaller the ADC can resolve.
Note that most commercial scopes (Tektronix, Agilent, etc.) costing less than $3000 have only 8 bits of amplitude resolution (i.e. “Y” or “Vertical” resolution).

As for the GBW of the amplifiers, note that they all vary with the gain of the PGAs. The PGA113 can have a gain of 50 and still exceed the DSANANO bandwidth. I guess if you want to measure micro volts, than this will not be sufficient. I can’t see using the DSONANO for use with very small signals because of the total lack of shielding, the input connector, and the probe arrangement. The DSONANO can be useful from a few HZ to perhaps 499 kHz with input signals greater than 10 mV. With 10 mV input signals the accuracy will not be very useful, but signal shape can be analyzed. To measure signals with reasonable accuracy, the input should be greater than 50-100 mV.

As for offset, refer to U5A in the DSONANO. The sole function of this circuit is to DC level shift the signal. The input to this circuit is via R15. The uC outputs a PWM here, which is integrated by R15, C12 and R16, C13 into a variable (depending on PWM) DC voltage to pin 3 of U5A. U5A functions as a buffer changing the DC level of the input signal from U5B before it goes to the uC ADC. If you replace U5 with a PGA, then the PGA has to have a variable offset input, which is pin 4 Vref on the PGA113. This is necessary even if the input is DC coupled to compensate for any offset and is probably also used for vertical positioning of the waveform on the LCD display.

Perhaps I was not clear about AC / DC input coupling. I suggest ONLY AC input coupling for the reasons I mentioned. DC coupling for the full range of inputs would not easily fit within the DSONANO (the complexity of the attenuator, requirement for +/- supply, level shift to match the 3 V ADC, etc.). A simple1nF capacitor in series with the 10 or 100 kOhm input resistor would work down to a few HZ.

The resistor I mentioned in the input is not to raise the input impedance, but to offer current limiting for the protection diodes in the PGA113. This is a very simple and inexpensive input protection circuit in case the probe is connected to a high voltage. The input impedance of the PGA113 is 10 GOhm (10,000 MOhm) with 5 pF capacitance. Changing the gain does not change this. Since most oscilloscope probes expect to connect to 1 MOhm , 5pF load, a 900 kOhm resistor (assuming a 100 kOhm input series resistor) is necessary from the input pins (2, 3) to ground. This is how the input impedance is defined. Note that there will be some small pF capacitors needed here to make sure the impedance is flat across the usable bandwidth. Most of the other PGAs have much, much lower input impedance and much, much higher capacitance.

This was in response to a few posters who asked about the possibility. You are correct that this would not make the DSONANO a 500 MHz Logic Analyzer, but limited to perhaps 100 to 300 kBs. I think that this would not be very useful because of the small screen and low resolution the DSONANO. But if there are people interested in this, it is a possibility. There are USB 8+ channel Logic Analyzer probes with similar performance for about the same price already, and they show the multiple waveforms on the large PC / Laptop / Netbook screen.

Perhaps what you need is an external battery pack. Model RC airplanes and helicopters have readily available LiPo batteries about the same size as the DSONANO which could operate it for 20-40 hours continuously. Of course this would more than double the thickness and weight of the DSONANO, cost $20-$40 and require a separate charger $20-$20.

SCHEMATIC from Slimfish of 6-22-2010

A few changes suggested:
• AC Couple both channels.
• Delete the 1 MOhm from IC pin 2. This also allows using a 1 nF or 0.1 nF COG (do not use X7R, X5R, Y5U, etc.) on pin2.
• R1, R2, C7 need to be 805 or 1206 for >200V capability. C7 and C? (47pF to GND) need to be COG types
• Delete C8, the ADC has enough capacitance. If a low pass filter is desired here, increase the value of the 100 Ohm resistor and use the input capacitance of the ADC to calculate R.
• Delete the entire Vref section (OpAmp and related parts). Connect pin 4 of the PGA113 to the same place as U5A pin 3 (R13 - C16 junction) in the current DSONANO.

I can help sourcing any parts. TI lists inventory here: focus.ti.com/docs/prod/folders/print/pga113.html

As I write this, The PGA113 is in stock at:
Avnet= 250 , Digi-Key= 98, Newark=139 , Farnell Asia= 519, Farnell Europe= 499 and Mouser= 86

The PGA 112 is almost the same part, but with Binary gain steps. Since this is for a DSO, I thought the simple 1-2-5 gain steps of the PGA113 would be more appropriate. The same vendors listed above have PGA112 in stock at larger quantities. I suggest you contact TI Asia. They can get you free samples and help with buying for production.


Hi shazam,

sorry if i bothered you with the circuit explanation of my last message. My intention was not to teach you but to show other people how the proposed circuit works. i’d like to emphasize that this series of posts are not because of my ego. I only want to contribute to enhance a product which can be very useful in my day work (when enhanced) and for many other people (like electronic enthusiasts).

The last circuit i posted had another error. This time was due to the drawing hurry (was done in 15 min). R5 and R? (i forgot to name it) are not grounded but connected to VREF. This is important, otherwise input can not cope with negative values.

Suppose the ADC can resolve 10 bit maximum with a VREF of 3V. That’s 2.9 mV/LSB. If offsets are in the range of 100uV, and we use a gain of 100 for the 10 mV/div, then we have a 10 mV offset which can be resolved by the ADC.

They cost thousands of bucks not only because the DC/AC resolution, but because of the sampling speed. And of course, for the functions they offer.

Both presented circuits cope with AC and DC coupling for the full range of inputs. And i think they are not complicated at all (even easier to adjust). And as showed, you need no split(±) supplies, otherwise, the PGA113 would not fit the bill (5.5V max).

If you get a 100kOhm resistor and use a 900kOhm in order to have a 1Mohm input then you have a resistive divider with a gain of 9/10. That’s fine when you have a signal with an amplitude smaller than 10/9 of VCC, which is not the case of DSO Nano, capable of -+40V with a x1 probe.

Again, in order to have a ±40V input with a x1 probe it’s necessary to atenuate the signal first. If you connect a x10 probe to the input, then signals will be very small and they have to be amplified (every mV is important).

There is no need to have a variable offset input when you can select between AC or DC coupling. The original scope doesn’t have a real AC coupling and the offset “simulates” and AC coupling by adjusting with the PWM the DC component. The PGA113 amplifies the signal in relation with VREF making the AC “simulation” a challenge programming effort in the case of this PGA.

You’re right, for two channel, up to 300 ksps are possible. But samples are not taken at the same time, so the aliasing probability is very high.

Thank you but no. What i need is a self contained oscilloscope for field use. And it’s not complicated to have an oscilloscope which enter low power mode if battery gets depleted (PGA113 has a software shutdown mode).

SCHEMATIC from Slimfish of 6-22-2010

A few changes suggested:
• AC Couple both channels.
• Delete the 1 MOhm from IC pin 2. This also allows using a 1 nF or 0.1 nF COG (do not use X7R, X5R, Y5U, etc.) on pin2. -> You’re right with the previous schematic. But this resistor is not connected to GND (see new schematic) and thus is needed anyway.
• R1, R2, C7 need to be 805 or 1206 for >200V capability. C7 and C? (647pF to GND) need to be COG types
• Delete C8, the ADC has enough capacitance. If a low pass filter is desired here, increase the value of the 100 Ohm resistor and use the input capacitance of the ADC to calculate R. -> The ADC input capacitance is about 5 pF. It’s very dangerous to count on such small (and variable) values to conform a low pass filter. But as showed on current DSO Nano it works…
• Delete the entire Vref section (OpAmp and related parts). Connect pin 4 of the PGA113 to the same place as U5A pin 3 (R13 - C16 junction) in the current DSONANO. -> No, you cant. VREF is a low impedance one (3.25 kOhm -see datasheet-) and hence the PWM filter will not function as intended.


Re: r2 schematic.

The problem with your r2 schematic is that the probe tip is now floating above Gnd by the value of Vref. This can influence whatever circuit you are measuring.

I think that is a REALLY bad idea.

So: I don’t see any way to have high input impedance without having a bipolar power supply for the input amplifier.


Hi dwayne,

every circuit you can design has an influence in the circuit under test. That’s why input impedance need to be constant.

The probe tip is NOT referenced to VREF, only the input impedance is. The GND of the tip is the same as the USB. So i don’t think it’s a REALLY bad idea. If you take a look in the PGA112 datasheet (pg. 36) you could see that this is an option used in many circuits. I didn’t reinvent the wheel again.

The circuit i proposed it’s a compromise between cost, simplicity, functionality and size. Of course it has it’s drawbacks. The main one is a DC offset in the circuit under test when measuring high impedance circuits (>100K). But if you tie the resistance to GND you will also influence the circuit towards GND (also a DC offset).

By the way, i built RV2 schematic & i doing some testing over it (frequency range, gain(f), offsets, etc). I’ll report as soon as i can.


Hi DwayneR and Slimfish,

DwayneR is correct. That is exactly why I suggested AC only, capacitive coupled inputs. To do this input circuit as a DC coupled, variable gain amplifier would cost a lot in terms of complexity, space, and money.

Regarding the input sensitivity mentioned earlier by Slimfish. The concept is to attenuate the input to accommodate the maximum P-P voltage you want to display on the scope. If you use a 10:1 probe, 30 V P-P becomes 3 V P-P, which is within the range of the ADC. With the probe switched to 1:1 the max input is 3 V P-P. By putting a 10:1 resistive divider on the input of the PGA113, these become 300V with a 10:1 probe and 30V with a 1:1 probe. If the maximum gain of the PGA113 is limited to 40 dB (gain of 100), then with a 1:1 probe the minimum input range is 300 mV P-P, which would be 37.5 mV per division (8 vertical divisions). This could be displayed as 30 mV / per division (with the extra 2 divisions not displayed, but available to see with Vertical offset).

By using a 3:1 attenuator in the PGA113 input, the input range would be:

10 V P-P/ division (80 V P-P for full display height) with a 10:1 Probe and
10 mV P-P/ division with a 1:1 Probe and max PGA113 gain of 100.

At the gain of 100, the PGA113 frequency response would be limited to about 300 kHz. At all other gains the PGA113 would exceed the Nyquist limit (500 kHz) of the ADC in the microcontroller.

If higher input voltage is desired, a 100:1 probe would allow a maximum 1kV input. Another possibility is to reduce the max Gain of the PGA113 to 10, reduce the attenuator and get 1 mV/ division input. I suspect that this would be useless because it would be very noisy.

Note that this design concept is based on using the protection diodes inside the PGA113 and requires enough series input resistance to limit the current to what the diodes can handle continuously at the maximum anticipated input voltage.

I think for this type of product, the 10V – 10 mV per division (100V Max input) input range using a switchable 1:1 – 10:1 Probe should meet most user’s needs.


Hi Shazam & DwaineR,

below is the schematic of a worst case scenario for DC offsets. V1, R1, R2 & R3 conforms a resistive divider. R4 & V2 model the RV2 DSO input (in the figure V2 is set to 0 -> connected to GND).

Let’s assume that DSO is not USB connected (otherwise R3 will be probably shortcircuited).

First case -> No DSO attached (ideal value)
OSC_IN = 900 mV
OSC_GND = 100 mV
OSC_IN - OSC_OUT = 800 mV

Second case -> R4 tied to OSC_GND (V2 = 0)
OSC_IN = 844 mV
OSC_GND = 155 mV
OSC_IN - OSC_OUT = 689 mV

Third case -> R4 tied to OSC_GND + Offset (V2 = 1.5V)
OSC_IN = 948 mV
OSC_GND = 51 mV
OSC_IN - OSC_OUT = 896 mV

Fourth case -> R4 tied to OSC_GND + Offset (V2 = -1.5). Equivalent to reverse connections in DSO
OSC_IN = 741 mV
OSC_GND = 258 mV
OSC_IN - OSC_OUT = 482 mV

Two conclusions are clear to me:
-every circuit you can design modifies circuit under test
-if VREF is non zero in the RV2 circuit, there is an offset which depends of the circuit under test. In the case presented was 200 mV depending of the form of measurement. If resistors were smaller (say 100K) offset accounts for a small 20 mV which is perfectly reasonable. But even if VREF is zero, there is some error (in this case the orientation of the DSO has no importance)

BUT (and that’s a big one):
-Are you usually work with MOhm circuits with a 1MOhm input? -> This is absolutely crazy IMHO
-Is it better to have a variable input impedance to work with (each scale a different measurement)?

As mentioned before, the circuit has it’s drawbacks.

Discrete variable input gain can be simply and easily done with solid state relays (like ASSR-1218 - 0.8€ @ 100 - mouser). The problem associated to them is size. But maybe is an option to consider. If VREF has to be 0, then bipolar power supplies are needed and the first circuit i posted can be used with minor modifications.

Side note: i think the purpose of redesigning a stage is to enhance it. Original DSO has DC coupling and 80 Vpp (selected to fit display range) for a x1 probe. Obviously you can modify some of the design constraints but i think you can’t redefine them all.


Edit: i forgot the schematic!!!

Hi all,

finally i got some time to do some test to the board i’ve built. The final schematic has been changed slightly in order to include a trimmer to ease the probe compensation. The designed PCB was designed with the time as the main constraint. So don’t expect a PCB design artwork here. A photo and schematic are included below.

In order to test the board, i used a Bus pirate (SPI commands), a multimeter, an oscilloscope and a spectrum analizer. The spectrum analyzer has an input impedance of 50 Ohm, so i also used a buffer between the PGA112 and the spectrum analizer.

Consumption (PGA + LMV321)
-Active: 1.4 mA
-IDLE: 0.5 mA

DC behaviour (DC measurements)
More or less as in the previous post. Expect a 5-10% error with 1% resistors and a usual circuit (R < 100K) under test.

AC behaviour
Tested first the compensation adjust with the trigger. Source was a square signal of 0.1 - 10 Vpp. It works, peaking is completely eliminated across tested frequencies (10 kHz - 500 kHz) and voltages. The x10 probe was not tested.
The frequency behaviour was observed for the 100 kHz - 1 MHz range. I would like to test with lower frequencies, but unfortunately, the sweep generator started @ 100 kHz.

When amplification was small (x1 - x32) the amplification gain was stable and the curve had 1 dB between peaks which translates into a 10% error for the full range. For the useable range of 100 - 200 kHz, the curve amplitude was < 0.3 dB which is approx. 4% of gain error.

For the higher ranges of amplification (x64 - x128) the amplifier was low pass filtering (approx. 3 dB @ 500 kHz).

I would like to post all the measurements in detail, but i don’t have the time to do the proper documentation. The circuit works (although it has to be tested with the x10 probe) and the results are very promising. Obviously, i would like to make a comparison between the actual DSO stage and the proposed one, but time is a scare resource these days, so i live that task up to Seeed or any of you with the proper equipment.

Needless to say, all the schematics and PCBs are with no license of any kind. Feel free to ask for the PCB & SCH file (protel) if you feel the need to.

P.S. All dB values are refering to a voltage signal, not to it’s power. Amplitudes are calculated as follows dB = 20 log10 (v).