I have not yet tested the digital inputs (probably by lack of digital probes )
But I have 2 comments:
Looking at the schematics I am a bit surprised by the values found on the input circuit.
The 11K resistors combined with the capacitance of the ESD protection diode (which is 110pF) makes a large lowpass filter. It is a pity as there are ESD diode that have very low pF capacitance at very low price.
This will surely lower digital inputs performance.
As far as I understand it, the inputs of the FPGA are configured in 2,5V input. The ESD protection diodes clamp voltage to 5V (7.3V max during transient). Donāt you think the inputs will be stressed if used on 5V logic (well perhaps not as the current is limited by the resistor)?
On the Quadās specifications, the voltage level for the digital inputs was not specified. It could be good to specify it before people burn their Quads.
After examining the Quad schematic and FPGA datasheet, I found out that pins 24 and 25 on the FPGA are used for Chan C and Chan D, respectively. As it happens, those pins are in what the datasheet calls ābank 3ā (page 49 of datasheet). Bank 3 inputs have an absolute max rating of 3.6V (page 91 of datasheet). Only banks 0 thru 2 have a 5V tolerance mode if you set VCCIO to 3.3V. This feature is not available for bank 3 (page 10 of datasheet).
I recommend not exceeding 3.3V on Chans C or D until a mod can be installed, possibly installing lower voltage ESD diodes at the inputs.
please help to state how did you find the diode is 110pF? i do not find the related statement in the datasheet . maybe your suggestion can help the designer a lot .
Thank you, you are absolutely right! I have just tested channel C and have overseen that not both diodes are ESD. The dealer didnāt mention that and I read actually only page 1 of the data sheet
Your warning must be repeated: with my diode there is no more ESD for one of the digital channels!
It would be not bad to try TVS diodes array in SOT-143 (SEMTECH SR3.3 or similar). The capacitance is a little more, but more reliable protection. In my opinion even it is not bad possible to establish with the minimum alterations in board (PCB).
Iāve just spent a bit of time looking for something suitable and my conclusion is:
a) 3.3V
b) SOT23 (or anything similar shape)
c) Low capacitance
Pick 2.
The only part thatās anywhere near is the RClamp0502 but thatās 5V, itās the wrong size and I have no idea where to get one.
Soā¦I was thinking: How about a hybrid solution?
Put a PESD3V3U1UT where the existing diode is, it gives 3.3V clamping on both channels plus ESD protection on one of them. Then add a 2-pin ESD protection diode across the input connector on the other channel (where the connector is soldered to the board). It doesnāt matter really what the voltage is for this diode so itās no problem finding something with single picofarad capacitance (or less).
Using two devices sounds a bit messy but if you try it let us know how it goes.
My thoughts on the USB3 device is it is very low capacitance and actually has a superior protection strategy in using ordinary diodes combined with a clamp diode so that the higher capacitance of clamp diodes is effectively shielded by the low capacitance ordinary diodes.
It is in a smaller pack which may make it a bit fiddly to fit. Iām not overly concerned about any differences in protection voltage as the series limiting resistor will lower fault current levels that could possibly get to the actual device before the main protection kicks in.
The problem is that the protection diode is on the same side as the series resistor.
Consider for example if there is 10V input voltage. Then the FPGA diodes will start clamping at 3V (koti.kapsi.fi/jpa/stuff/pix/dso_ ā¦ urrent.png). Because the voltage is clamped at 3V, absolutely no current will flow to the 5V protection diode. Such a diode is completely useless, it wonāt do anything until the FPGA input is already broken.
Iām not sure if 3.3V protection diodes would be effective either. The FPGA input diode forward voltage will probably rise a bit when the current rises, so it might still help something.
Optimal solution might be replacing the R41 and R42 with a series connection of two resistors, with the clamp diode in between them. But this is probably quite difficult to do.
Yes. Youāre right that the input resistor configuration doesnāt allow for best protection here.
I thought though that the existing external diodes were also higher stand-off than internal and so it would not be making anything worse.
Iām no expert but I think that main risk is during ESD transients where the situation is quite complex with the transient conditions being significantly different from what a simple stable low voltage analysis indicate. So for sustained low voltage overload the internal will be taking the current but the series resistance will be fairly effective in limiting energy. Obviously putting on medium voltages for sustained periods is not going to do the series resistor much good depending on its rating but that is a low risk when using these inputs for what they are intended. For high voltage pulse the external diodes may help redirect the energy depending on the transient behaviour of the internals and provide better protection
If the external diodes have high capacitance, they ruin the digital input bandwidth. Because the digital inputs otherwise go directly to FPGA, they should be good for up to 72MSps without the external diode.
The TPD2EUSB30 pack I have ordered is designed for protecting 6GB/s USB 3 connections and has 0.7pf capacitance to ground. It should have negligible impact on achieved bandwidth.
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