Hi,
This is about hardware 2.6, SYS 1.41, APP 2.45.
I found a timeline difference in digital probes and analog probes. Attached captures shows the wave forms of one signal point taken by all 4 probes. The rising position has to be same but you can see there is a visible difference, say 5 or more dots on screen. I think it’s a software bug in display position since the delay keeps around 5 dots in any sweep time. Hope it’s fixed in updates.
Best Regards,
Andy
I can not attach images to my previous post. It ignores the uploads. Why???
I can confirm your findings; I ran into the exactly same problem when making the Logic analyzer app. I ended up solving it by clocking the ADC faster than what would be needed for the samplerate.
The delay is caused by the AD9288 ADC-converter conversion time, and is exactly 5 samples. More delay may be caused by the slow response of digital inputs due to high capacitance ESD diode used.
It would be trivially simple to solve by modifying the FPGA code (add a 5-stage register chain to delay the digital inputs), but unfortunately recompiling it requires a $2000 license. It would obviously be the responsibility for the original designers to make this fix, but judging from the current FPGA code quality I’m not looking forwards to it…
Hi jpa, Thanks. Your description made it so clear. I was capturing the integrity of signal timings though it needed to put C and D probes to the earlier signals to look like they were in correct position. Hope this toy becomes a real weapon soon. I like this very much.
Thanks,
Andy
It should be more reasonable or free to grow DSO quad to a “gooduino” product.