Dear Seeed,
Now that FPGA tools from Lattice are available, it’s becoming possible for us to modify the FPGA image.
Could you please provide the bootloader source code in order to show how the FPGA configuration is currently implemented? Also FPGA ver 2.61 sourcecode would be appreciated (currently only ver 2.5 is available).
Its been released for a while: viewtopic.php?p=6694#p6694
I went to the Lattice site downloaded the ICEcube2 software but it needs other stuff to open the project.
Then I ran out of time to find out what else I needed.
If you know what is required it would save me time looking around their hard to navigate site.
Hi,
I just downloaded the Windows version and requested a license from:
latticesemi.com/products/des … ce=sidebar
Then I followed the instructions in viewtopic.php?p=7240#p7240
I was able to compile FPGA 2.5 and it works on my device.
BTW. Maybe I missed something, but I could not find the bootloader code nor FPGA 2.6 in that post. Just SYS, APP and FPGA 2.5.
Oops, my bad. Early morning dyslexia.
I read it as you wanted the source for the FPGA not a specific version.
I don’t know if 2.61 is released much like I don’t know if Hardware2.7B is released.
Pretty closed documentation for open source IMHO.
Maybe we need a new name for this, like, CTWOI source. (Closed Till We Open It).
Re compiling the 2.5 code, nope. not working for me and I got the license via email.
It allows me to open files but that’s it. It won’t display any open files and everything is greyed out so I can’t do anything at all. Effectively I see no change between an open project and no project. When I get some free time I’ll look into it.
Do they release licenses to engineering students? Because I asked one a month ago and no one replied.
I’m submitting another request right now…
I got a license for the windows one free (strangely, with a wrong nodelocked (flexlm) host ID (ethernet MAC), but since it was in a VM I just changed it to match)
I was able to fully compile the available 2.5 FPGA code into a bitstream. But I don’t know what’s changed between 2.5 and 2.61… Can we get a list of changes, or its code? Please 
?
Loading custom FPGA binaries from the flash drive (without overwriting the default FPGA image) seems to be a bit complicated. For some crazy reason, the SPI port of the FPGA chip is not hooked up to a SPI port on the STM32. Bitbanging SPI is ordinarily quite simple, but apparently the FPGA expect a minimum steady clock of 1MHz. It would be really interesting to see how this is solved in the bootloader, or if they just ignore the specs.
With a tight internal loop, and doing some tricks, maybe (72 cycles per byte transmitted at the minimum speed - 9 cycles per bit), I don’t think it would be too bad…
Probably that’s most of the reason the DFU is closed - that would be a clever bit of code.
I make no promises about this, but it might work. It’s been a long time since I’ve looked at assembly…
begin and end have to be 4 byte aligned, and the end should include the necessary 0 bits (at least 49 of them)
[code].syntax unified
/* R0 is current flash memory read address
r1 is end of flash
r2 is 1
r3 is current 4 byte
r4 is next 4 byte
r5 is PB11 set bitband address
r6 is PB11 reset bitband address
r7 is PB13 data bitband address
sck starts high
*/
#define P_BASE 0x40000000
#define BBP_BASE 0x42000000
#define GPIOB_OFFSET 0x11c00
#define GPIOB_BASE P_BASE+GPIOB_OFFSET
#define GPIO_ODR_OFFSET 0x0c
#define GPIOB_ODR (GPIOB_BASE+GPIO_ODR_OFFSET)
#define GPIO_BSRR_OFFSET 0x10
#define GPIOB_BSRR (GPIOB_BASE + GPIO_BSRR_OFFSET)
#define GPIO_BRR_OFFSET 0x14
#define GPIOB_BRR (GPIOB_BASE+GPIO_BRR_OFFSET)
#define BB_GPIOB_ODR(n) (BBP_BASE + ((GPIOB_OFFSET + GPIO_ODR_OFFSET) * 32) + (n4))
#define BB_GPIOB_BSRR(n) (BBP_BASE + ((GPIOB_OFFSET + GPIO_BSRR_OFFSET) * 32) + (n4))
#define BB_GPIOB_BRR(n) (BBP_BASE + ((GPIOB_OFFSET + GPIO_BRR_OFFSET) * 32) + (n4))
/
#define LOAD_ADDR(r, addr) mov r, # (addr & 0x0000ffff)
/*; movt r, # (0x0000ffff & ((addr & 0xffff0000)>>16))
*/
#define LOAD_ADDR(r, addr) ldr r, =(addr)
#define SET_SCK_LOW str r2, [r6]
#define SET_SCK_HIGH str r2, [r5]
#define LSR_DATA lsrs r3, r3, #1
#define SET_DATA str r3, [r7]
#define DOBIT SET_SCK_LOW ; SET_DATA ; LSR_DATA ; SET_SCK_HIGH ; nop; nop
/* THUMB2 function definition
void fpga_load(void *begin_addr, void *end_addr)
*/
.section .text
.global fpga_load
.thumb_func
fpga_load:
push {r4-r7}
LOAD_ADDR(r5, BB_GPIOB_BSRR(11))
LOAD_ADDR(r6, BB_GPIOB_BRR(11))
LOAD_ADDR(r7, BB_GPIOB_ODR(13))
SET_SCK_HIGH @ should be high since reset
mov r2, #1
ldr r3, [r0] @ 4 cycles - 2 read, 2 wait state
rbit r3, r3
@ begin critical timing - 9 cycles total per bit max
loop:
DOBIT @ bit 0
DOBIT
DOBIT
DOBIT
DOBIT
DOBIT
DOBIT
DOBIT
DOBIT
DOBIT
DOBIT @ bit 10
DOBIT
DOBIT
DOBIT
DOBIT
DOBIT
DOBIT
DOBIT
DOBIT
DOBIT
DOBIT @ bit 20
DOBIT
DOBIT
DOBIT
DOBIT
DOBIT
DOBIT
DOBIT
DOBIT
SET_SCK_LOW @ bit 29
SET_DATA
LSR_DATA
SET_SCK_HIGH
adds r0, #4
nop
SET_SCK_LOW @ bit 30
SET_DATA
LSR_DATA
SET_SCK_HIGH
ldr r4, [r0]
SET_SCK_LOW @ bit 31
SET_DATA
cmp r0, r1
beq finished @ from cmp up above - if finished, jump and be done
SET_SCK_HIGH @ if not finished, get here - no branch = 1 cycle
rbit r3, r4
b loop
finished:
SET_SCK_HIGH
pop {r4-r7}
bx lr
constants:
[/code]
True, that’s probably how the bootloader does it as it has everything in internal flash. I have to load the FPGA image from the external flash filesystem, so I need a FIFO and to do the bitbanging using DMA. I already got the filesystem read speed to 1.5MBps from the 300kBps achieved by the BIOS.
Is that with DMA, or is the CPU busy doing that read?
As long as the file isn’t fragmented on the flash, you can stream it with READ_DATA_FAST …
Are you sure about this? I just had a look at the datasheet for the STM32 and the PB12 - PB15 ports are accessable as SPI2…
Mmmm, second thoughts, the schematic (DSO203 v2.6) shows the SPI port on the FPGA connected to PB10 - PB13. Now that seems a bizzare oversight!
Is the schematic wrong, or did the HW designer really stuff up!
The schematic seems to be accurate.
Here is my implementation of bitbanging the SPI on those pins:
github.com/PetteriAimonen/QuadP … ime/fpga.c