AC101 codec clock and sample rate(s)

[dana.myers]

I’m experimenting with the ESP32-Audio-Kit, which is based on the ESP32-A1S from AI Thinker. This module integrates an AC101 CODEC, and my experiment is directly programming the AC101 (rather than using ESP-ADF or other library).



From the AC101 User Guide, I’ve gathered that the AC101 CODEC is intended to run at a fixed clock rate, section 11.2 says:

The system clock(SYSCLK) of AC101 must be 512*fs(fs=48KHz or 44.1KHz). So the system should

arrange the divider to generate 24.576MHz for audio clock series of 48KHz or 22.5792MHz for series of

44.1KHz

.



and the sample rate is selected by Reg 06h_ADDA Sample Rate Configuration Register and there are actually two sequences - the 44.1ks/s sequence and 48ks/s sequence, where the sequence consists of integer multiples/dividends. I want to sample at 12ks/s so I ended-up programming the clock PLL for 512 * 48kHz, setting Reg 06h for 12000s/s sampling rate. I was amused to find that the resulting I2S stream is still at 48ks/s with groups of 4 samples. So the codec appears to be sampling at 12ks/s, but repeating each sample 4 times. In my software, I take every 4th sample, since I believe the codec has effectively decimated the bandwidth already.



Is this what I should expect? Is there some programming trick for the AC101 to reduce the inbound I2S traffic to just 1 sample per sample?



Cheers and thank you,

Dana K6JQ