I know BenF has looked into the possibility of running at 2MS/s before but I would love to get that little bit more out of the DSO Nano.
Looking at the MCU datasheets, it appears possible to run ADC1 and ADC2 in fast interleave mode to net a 2MS/s overall speed providing that the MCU clock is set to 56MHz and ADC clock is 14MHz. The ADCs should then sample 7 ADC clocks apart i.e. at equal intervals as opposed to being bunched up. This does force the use of DMA transfers however.
With that said, at 56MHz, is there a bottleneck that prevents such operation? Would a reduced buffer size - say 2048 help? I could live with that.
BenF, did you drop to 56MHz to bring the sample rate up to 1MS/s? Fantastic work on the firmware by the way!
An option I would like included is a menu option to turn off the DAC output completely. Currently I set the freq low and duty cycle to 0 to stop the visible interference it causes at low V/div settings. Maybe it would reduce power consumption a little too?
An option to stop the DAC sounds like a good thing to me, both in terms of interference and power consumption. User’s would have to remain aware that U9 (74HC125) would still have a low or high level output and could still be damaged by voltage applied to the Fout jack CN3.
The Cortex M3 used in the Nano does not have a DAC and so we’re limited to a PWM square wave for the output signal. Power consumption will be negligible when not loaded. Setting duty cycle to zero will disable PWM and ground the output. If you like to keep if off by default, you can save this configuration as part of your power on profile and then use quick select to set duty cycle to 50%.
The link below has more information on the constraints related to sampling speed. 1 Ms/s is the upper limit with the current design.
Zero pulse width saved to power on profile does the job nicely.
So I gather from the previous postings that it is the trigger point calculation that really unhinges the jump to 2MS/s?
