Programming the ESP32C6 LP Core

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The C6 has a full blown RISC-V LP core, not the finite state machine ULP core of other ESP32s:

  • Utilizes a 32-bit processor based on the RISC-V ISA, encompassing the standard extensions integer (I), multiplication/division (M), atomic (A), and compressed (C).
  • Interrupt controller.
  • Includes a debug module that supports external debugging via JTAG.
  • Can access all of the High-power (HP) SRAM and peripherals when the entire system is active.
  • Can access the Low-power (LP) SRAM and peripherals when the HP system is in sleep mode.
  • LP-Core code can be written in C or assembly.

https://docs.espressif.com/projects/esp-idf/en/stable/esp32c6/api-reference/system/ulp-lp-core.html

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