Success!
Reporting back to let others know there’s a solution to this problem. The main issue is the bit ordering that the NFC shield sets to LSB. Now, when the ethernet tries to communicate with the chip, it basically reads nonsense.
We hence modified the read and write functions in PN532_SPI to set the order to LSBFIRST prior to any comm with the shield (right before setting the own pin to low) and reset it to MSBFIRST after the access. That way we assure the ethernet link receives data as expected.
Furthermore, it is advisable to set the SPI bus clock to 4MHz (default for the NFC shield is 2MHz, 5MHz is max, according to a comment in the code) by setting the clock divider to 21. A higher bus clock is usually better for the ethernet chip’s performance. As a side note, it’s not necessary to set any SPI pins manually, this is all done internally by PN532 and the ethernet2 lib.
If it’s of interest to somebody, I’d be happy to elaborate in more detail.
Cheers,
o.