This board does not have enough gpio pins IMO. Considering there is the extra Cortex-M4, there should be at least 32 more GPIO pins (that’s just 2 ports) directly connected to Cortex-M4. Why else should I consider this board compared to, for example, Beaglebone Green that has 2 embedded PRUs and plenty of GPIOs?
How does the data transfer (memory access) between the A7 and M4 works? Would it be possible to mmap the M4 SRAM from within Linux userspace and read/write data? If no, how the data exchange between the CPUs works? If yes, what is the data throughput and what are the latencies of the M4 when the M4 SRAM is accessed by both M4 and A7 at the same time?