Since we have a lot to FPGA logic to spare, the FPGA could even catch the preset point in your project with something like this
[code]
– Start some counter somewhere
sig_preset_reached <= ‘1’ when ADC_sample > PRESET else ‘0’;
preset_capture: process(sig_preset_reached)
begin
if rising_edge(sig_preset_reached) then
– stop counter and output count
end process;
[/code]
The first part (combinatorial) can easily run in less than a ns, and the counter can be connected to the main sampling clock.