Dear dida.poli
I just get my new DSO203 version 2.82
Would you please give me step by step guide how to flash last realize of WC firmware (6.0)?
Thank you!
Dear dida.poli
I just get my new DSO203 version 2.82
Would you please give me step by step guide how to flash last realize of WC firmware (WC 6.0)?
Thank you!
Dear WILDCAT
I have DSO203 and I need functionality from it… Like FFT…
Would you please give me advise which firmware fit for it and step by step guide for FIRMWARE update?
my mail is: muslimens(at)gmail(dot)com
Thank you!
@muslimens
Worked for me with “Windows 10” but not with Windows XP
[list]
Hello dida!
Thanks for reply!
- You told me " copy app1.hex " - just only 1 file from that big folder… that is enough ?
- And what happens if I saw " app1.err " - my device became bricked? Could I restore it in such case?
Thanks again!
- Yes. The rest is for advanced use. (to program additional features to WC e.g.)
2.) estimate:
[list]
Dear folks,
just wanted to report a minor bug I came across in wc3.4 and wc5.1 (just updated to 5.1 - fantastic work wildcat!!!).
My setup:
HW 2.70 with DFU 3.11C, sys 1.52, alterbios 0.4 (stock except alterbios)
Minor bug I just found:
When in “A&B” trigger mode, signal sometimes freezes (Ch.B) or zeroes (Ch.A). Solution is: leave “A&B” trigger mode and enter it again.
How to reproduce:
- input signal, e.g. wave out (easy to reproduce this way)
- cut input signal (for testing: set wave out to “OFF”) and reactivate again
after a few tries (in quite some cases after first try) channel A shows flat line / channel B freezes display
Leave “A&B” trigger mode and enter it again: everything is fine again.
Just wanted to report this, but is not a big problem.
Cheers
Thomas
I’m afraid I have not been able to duplicate this, tried various timebases, trigger types, etc. Might help if you describe in detail exact settings used such as timebase, trigger types, trigger levels (try auto trigger), any other functions active at the time such as trigger delay, decode modes, etc, as well as which channel you are turning the source signal on/off. Does this only happen when you FIRST engage A&B mode? After you re-engage can you still reproduce the issue by shutting off the source?
One possibility with V5.1 behaving like this could be memory allocation issues like the one when this version was loaded on HW 2.81. When loaded on earlier devices, for some reason the problems did not seem to exist, but it was not clear to me at the time why this was so. Odd triggering issues like this were typical with V5.1 loaded on HW 2.81. After working on the upcoming update (V5.2/V6.1) the same memory issues started creeping up on early devices. These have now been resolved, am in the process of finishing a chart mode update, and will be posting this shortly. If I don’t find anything else in the meantime, I would suggest trying the next update to see if it fixes the problem.
V3.4 however did not have any memory allocation issues, so if this existed in that version, would point to something else, also tried another older device with the original V5.1 loaded and still could not duplicate this. Finally, you could try resetting the configuration by removing the WPT file (save it so you can return it to the device afterwards), corrupted config files can sometimes cause strange behavior.
Dear Wildcat,
thanks for your quick reply. After reading your words, I suspect that I might have a hardware problem. After investigating a bit further, I was able to break it down to the use of “NORML” trigger mode, as I usually leave it to “AUTO” and it gets switched to “NORML” in A&B mode, just as stated in your manual.
Attached my used config file and four screenshots, where I used “NOISE” as signal input (in real life I came across this while measuring PWM signals). It has been the same in wc3.4 and wc5.1 (factory app doesn’t support A&B mode, so I cannot test with that). In all screenshots the signal generator was connected to both channels. “NOISE” I only used because it’s directly next to “OFF”, the problem persists with any signal form.
When switching from TR D (rising edge) to A&B, channel A is dead most times (nearly always)
When switching from TR A (rising edge) to A&B, channel B is dead (sometimes)
When cutting input signal while in A&B (rising edge) and activating signal again, both channels are dead (most times)
Seldomly I am able to display both signals in A&B mode, but sometimes this is the case (see IMAG007.bmp, but it took about 10 tries to achieve this).
In AUTO mode, there’s absolutely no problem. Also, as long as the signal isn’t cut off, it doesn’t freeze once it works.
Possible causes I currently see:
- my device has a hardware fault that leads to faulty triggering in NORM mode
- my config file is corrupt
- it’s normal for this mode, and I misunderstand the concept behind this
Please don’t investigate too much, as I see it as a minor bug (in fact I accidentially activated A&B mode in wc3.4 and wondered why my channel suddenly seemed dead, mostly I use AUTO trigger mode for single channel). Unfortunately I have no option to test a different DSO203, as I only have this one available.
Again, thanks for your great work!
Looking at your screenshots, I can see why you are getting these results, at least with the waveforms you are displaying:
You are using the auto trigger mode on a wave with a significant DC offset while in DC coupling mode. This pushes the waveform up away from the baseline. When not triggered, the auto trigger function looks for crossing events at the baseline, so it doesn’t “see” the wave riding on the DC offset above, unless it catches some transient while switching functions. Once triggered, it depends on the displayed waveform to establish a mid-point reference but in normal mode, no signal is displayed until it is triggered, unlike in auto mode.
The obvious solution is simply to shift the coupling mode over to AC. Notice that ALL outputs from the internal generator have this DC offset.
Another solution, if the DC offsets are desired to be displayed in DC coupling mode, is once triggering level is established with AUTO trig and waveforms are properly triggered, freeze the setting by long pressing button 2, this shifts over to manual mode. Or just simply move the trig cursor to the proper level in manual mode. When manually shifting the trigger level in A&B mode, both channels move together, so it may be necessary to shift triggering source to one or the other channel to set that level, then shifting back to A&B mode.
Setting auto trig with a short press of button 2, then following with a long press to freeze the setting is a sequence I use extensively with these devices, since auto trig can cause the trig level to fling around a lot in trying to follow rapidly changing waveforms.
Dear Wildcat,
I see, the problem was that I misunderstood the concept, and there’s no system fault at all. Using manual trigger level truly solved the problem for me.
For me it is absolutely desirable to display pulsating DC “as is”, as currently I mainly measure PPM and PWM signals in lipo powered model flight hardware (that’s why I chose a pocket device that I can use at the flying fields) and the like and need to see the true voltages next to pulse width and frequency, so AC coupling is not a solution for me.
Many thanks for your efforts and pointing me to the right direction. Again have learned something!
Greetings from germany, keep up the great work
Thomas
New updates V6.1/V5.2:
Mainly updates CHART mode to fix improper ADC operation at slowest timebases. Changed chart buffer to oversampling and added selection of either averaging or oversampling (peak hold) modes. Select while in chart mode with menu on timebase adjust, short press left toggle center to access chart mode auto file write, press again to access buffer mode. Change with left toggle. Defaults to averaging but selection is saved with config files.
FPGA based OS function proved to be not well suited for slow chart operation, so used software instead. Since this does not depend on FPGA hardware, the revised chart mode is compatible with older versions as well and so is also included in V5.2
Oversampling factors vary from 100X at 0.1S/div to 600X at 10Min/div. eg: at 10Min/div, the device obtains 30 readings per second for a total of 600 during the 20 second span for each the 30 steps in one division (600sec/30steps), then either averages them to produce one sample or stores the + and - peaks for display. Averaging will reduce noise while oversampling captures any noise or signal spikes.
Other fixes: (See readme.txt for more info):
V6.1:
-Fixed long buffer mode not always initiating when recalled from a config under some conditions.
V6.1/5.2:
-Updated detector mode frequency display.
File is broken. Download randomly 44-106kb zip. Tried on computers with win 7, 8.1 and 10.
Just tried to access the files I posted, they downloaded OK for me.
SEEED may be updating their web site, if you go to http://www.seeedstudio.com/forum/index.php for example,
the section under “DSO” is blank. Several others are as well. Perhaps this has something to do with
failed downloads.
I noticed an unusually large amount of downloads for these files, for being posted for only 1 day, perhaps
others are having difficulty as well and re-downloading the files repeatedly, bringing the counters up.
Will be keeping an eye on this. Will try re-posting if necessary…
Uploaded files to another site, if unable to download here:
<LINK_TEXT text=“http://www.files.com/shared/5743a34791b … atV5.2.zip”>http://www.files.com/shared/5743a34791bd4/WildcatV5.2.zip</LINK_TEXT>
<LINK_TEXT text=“http://www.files.com/shared/5743a348825 … atV6.1.zip”>http://www.files.com/shared/5743a348825b0/WildcatV6.1.zip</LINK_TEXT>
Also forgot to include the W1.1 FPGA code in V6.1 (Required, if not already installed from previous update, to use full speed oversampling mode on hardware V2.81 and up ONLY)
<LINK_TEXT text=“http://www.files.com/shared/5743b0ac266 … 20FPGA.zip”>http://www.files.com/shared/5743b0ac2666a/W1.1%20FPGA.zip</LINK_TEXT>
Thanks Wildcat again for the updates.
I've asked MiniDSO for details about HW v2.82 this is what i've got:
"HW2.82 is only a small part of the layout is different, the same hardware"
I also asked about DFU v3.46C and got they said it is HW2.81 compatible. They also provided the rom to flash the STM like i requested:
http://www.minidso.com/forum.php?mod=viewthread&tid=1202&extra=page%3D1
I have now updated to DFU v3.46C from v3.45C and here's the funny part:
Before as you know on my main intel i7 win10 laptop when copying your application it would disconnect the DFU drive while copying making it impossible to install your application. (smaller files like FPGA are able to installed normally)
That's why i've used and old winxp desktop machine which worked fine because it will copy the files without disconnecting the DFU drive.
A week or so ago i installed your v6.1 when it was running DFU v3.45C with that winxp system.
Today i updated to DFU v3.46C and while the app1.hex copies fine like expected, it will always give .ERR and the application will not install. I've tried different versions and stuff, always giving the same .ERR on app files, but then i went to my brother's core duo laptop running win10, and guess what? It installed it without an issue.
I got this idea because i saw a post with someone with a hw v2.82 having the same issue here, and he made a thread over minidso forums, saying he successfully installed your app on a win10 machine.
So from what i understand they managed to f**k up DFU even more that before. What do you recommend to do with this issue since more people are having this type of incompatibility with different systems. I suggest that i make a thread over minidso to get their attention hopefully to get it fixed with a newer DFU update. What do you think? You might say update is difficult but with a cheap USB to RS232 adapter and the tutorial i made it is very easy for anyone.
I wouldn’t be too hard on the factory guys, Microsoft likely changed, on purpose just to screw things up, the way these (to them obsolete) volumes are accessed in their new Windows versions.
It would seem though there should be some way the DFU could probe the host system to find out what version of Windows is accessing it, then readjust itself accordingly. Or simply have a menu so the user can select the proper Windows version.
Not sure though how many users are willing to open their devices, solder some pins and attach a serial connection to their PC in order to do this. On a bricked unit, yes, but on a perfectly good device it seems much simpler (and safer) to just find an older computer to upgrade with.
DFU always has been kind of funny. I once had a problem (not with wildcat, but with gabonator) reinstalling: always got an .err. Needed to reinstall because by accident I overwrote part of the code. Solution was: install something completely different into the same slot, and then try again. Which in fact solved the problem!
Was not Win10 though, but Win XP (my older 2.70 device with DFU 3.11C). So in case reinstalling whatever doesn’t work, one could possibly succeed by following that procedure.
Have fun 
Thomas
Yes i get your point, but it is really weird that only this specific device has such an incompatibility problem, where you saw it doesn’t seem to be OS specific but rather than system specific. Also it will still affect new devices sold to customers, and i think they might not being even aware of this issue. I thing i should just make a thread to see what they have to say about it at least 
Yes i was thinking to do something like this but couldn’t find the original app on that (winxp) system so i happened to try the other win10 system and it worked. If i remember i will try this next time to see if it makes a change or not Another thing worth noting though, it actually required me to re-install the fpga after installing wildcat on that win10 system, where i had already installed it multiple time successfully on the winxp system multiple times. What’s up with that?
The DFU update you downloaded from the MiniDSO site is a complete ROM update, including the V1.64 Sys and the original FPGA and LOGO, along with their APP, that’s why the FPGA reverted to the original.