Wishes especially to the workers, who brought it with their outstanding work and time and extra time :shock: to the actual status. :!: :!:
I found the product by luck and would’nt have bought it without reading “all” the pages of this blog. Thanks.
I hope it supports me during my technical study.
I have made the test (hopefully in the way you need, but only with one channel :roll:). I would interpret no ADC problem at room temp. I would have uploaded the images, but I have to learn it first. Put them in later if wished ;
Again thanks a lot.
(Mayby later, end Jul.16, when I have to finished my master work (examination Sep.16), I want to give some time for work and support back.)
Check with the device in full speed buffer mode. With the same signal displayed as on your post, keep pressing the right toggle center button (switch #6) until the bottom notification zigzag turns blue with an orange border (the area under “save file” in your screenshot). The problem mostly shows up in this mode and in channel A. You could check Ch B with the same settings just to make sure. Also, raising the gen output level (Vo 1.3V on menu) to around 2.5V and using the .5V range should minimize waveform noise.
Thanks again for the feedback. I think the results speak for themselves.
For those with issues with their DAC using V5.1 and it’s FPGA with HW 2.81 an alternative would be to use the FPGA supplied with V5.0 . This should work fine with V5.1 and HW 2.81 with the problem DAC’s, and while it would not have full speed sampling, it would provide improved level based triggering accuracy and overall triggering stability at the fastest timebases over the factory FPGA. It would also provide auto mode freerun behavior selection.
The touch 202 is a newer device and has good eyecandy but less analog bandwidth. However, I can swear by the DSO203 I own for a some time now. If you need more info, please open another thread so as not to divert this thread topic.
Hi, WildCat! I want to thank you for excellent operation and to wish a good health!
I updated the DSO203(HW 2.81 SYS1.64 DCU 3.43) on version 5.1 and used FPGA 1.1. I checked operation of an oscillograph in the mode of the complete buffer. Results are visible on a photo. Problems begin in the AC1V,AC2V,AC5V mode. In channel B there are no such problems.
This is not an issue with the ADC. This is noise picked up by the preamp. Noise from the ADC would show up the same on the screen regardless of the vertical range used.
I had a similar problem with my unit, causing thickening of the trace on ChA in full speed mode similar to yours. Turned out to be a bad ground. The metal frame that holds the LCD is grounded by a stick-on metalized tape to one of the input or generator output jacks and it was making an intermittent connection. You could move the plugs around when inserted into the jacks and the noise would cut in and out.
In any case, this is definitively noise picked up by the front end in the input section. The device switches in a different op-amp when set to ranges of 1V/div and above. Looks to me like noise from the rest of the circuitry is being leaked into that section, possibly from a bad ground, capacitive coupling, power supply issues, etc… ChA seems more susceptible to this for some reason, probably because of the location of the circuit traces on the board. The LCD is also a prime cause of radiation into the circuitry if it’s frame is not properly grounded, since it covers the entire board. The grounding method is rather poor, relying on simple pressure of part of the frame onto the metalized stick-on tape.
As I mentioned previously, the full speed mode will, by it’s more sensitive nature more readily reveal any noise, whether generated by the circuit you are monitoring or generated inside the scope itself. This is in fact part of what makes it useful. Also, loose or defective probe plugs making a poor ground connection where inserted into the input jacks can cause problems like this.
You could try reverting to an earlier FPGA, it’s possible the extra circuitry for the full speed mode is causing an increase of noise on the supply lines, and an increase in this noise, but since it’s only appearing on some of the ranges, I suspect that some hardware issue in the preamp is causing this, and that it would also show up with earlier FPGA’s, though possibly to a lesser extent. Notice that the “spike” part of the noise shows up in your screenshots even when not in full speed mode.
You have to take the unit apart, of course. On the front side of the board, the frame of the LCD presses against a small wire mesh covered square that is glued to the Gen Out jack body. I first tried to solder a wire directly from ground to the LCD frame but the metal it was made out of didn’t seem solderable. I was reluctant to apply too much heat for fear of cracking or otherwise damaging the display, so I just soldered a piece of thin copper over the wire mesh and onto the jack which built up the thickness and allowed for a better contact with the LCD frame.
I just looked at pictures of some earlier hardware versions, and these seem to ground the LCD frame in a different location. There appears to be more than one display version being used, so not all units may be the same.
The only thing I can think of is maybe you have inadvertently pressed button 2, which sets the trigger level to AUTO. In this mode, cycling though the trigger menu with button 4, the “LEV” sub menu will be skipped. Press and HOLD button 2 until it beeps, this sets the trigger level to manual and moves the focus to the LEV sub menu. To the right of “LEV” will show “MAN”. In manual mode, button 4 can also be used to select LEV. When in auto level mode, MAN changes and cycles through 1/2, 3/4, then 1/4 with each SHORT press of button 2.
Good health to you, Wildcat! Recently bought a DSO DSO Quad. He wanted to update the firmware and searched the Internet, found. Before I HARDWARE was 2.81 and was 2.6. I do not understand what happened. Then set your firmware, it became much better. Can I create one that is not so. How to change the firmware properly? How to make CH(A) in the middle? When connected to a computer, he does not see it as a drive, format offers, but ends up formatting error. I am just learning. Help me please.
Photos from my mistakes DSO Quad could not upload here, but I can send them to you by mail.
Just now noticed some issues with my latest updates loaded on hardware 2.81 devices: These involve problems like loss of some meter functions or meter display after saving config files, possible temporary loss of triggering or other random problems.
The fix involves increasing RAM allocation from 48K to 64K and increasing the call stack from 8K to 16K. Since HW version 2.81 is the only version with 64K of RAM available, this would NOT be compatible with any other previous hardware version, nor would it be necessary since these problems do not appear to exist with earlier HW 2.60 and 2.70 devices.
Possibly, the larger buffer size needed for the 8MB drives is causing the stack corruption; unknown at this point if HW V2.72 is affected, these were the first to have 8MB drives. All my previous devices are of V2.70 or earlier so I can’t check those out.
I have always taken the older version devices out for field use, so this went on unnoticed until now. Will be taking the 2.81 unit for use from now on.
Will be posting an update to fix this shortly, need to check things out more thoroughly. However this will now necessitate different versions for new and older devices. Again, older HW 2.70 and earlier units should work properly with all posted versions.