I should also mention that after the firmware update, it stays connected with later versions of Windows.
Hi, wishes to all, new to the forum. 
Wishes especially to the workers, who brought it with their outstanding work and time and extra time :shock: to the actual status. :!: :!:
I found the product by luck and would’nt have bought it without reading “all” the pages of this blog. Thanks.
I hope it supports me during my technical study.
I have made the test (hopefully in the way you need, but only with one channel :roll:). I would interpret no ADC problem at room temp. I would have uploaded the images, but I have to learn it first. Put them in later if wished 
;
Again thanks a lot.
(Mayby later, end Jul.16, when I have to finished my master work (examination Sep.16), I want to give some time for work and support back.)
ok I found it,…
[attachment=1]20160323_DSO203_channel1-test.jpg[/attachment]
[attachment=0]20160328_DSO203_Software 2 Boot serial-covered.jpg[/attachment]
Thanks for the feedback.
Norbert:
Check with the device in full speed buffer mode. With the same signal displayed as on your post, keep pressing the right toggle center button (switch #6) until the bottom notification zigzag turns blue with an orange border (the area under “save file” in your screenshot). The problem mostly shows up in this mode and in channel A. You could check Ch B with the same settings just to make sure. Also, raising the gen output level (Vo 1.3V on menu) to around 2.5V and using the .5V range should minimize waveform noise.
Thanks again…
With 5.1 no problems whatsoever.
Wildcat, thanks once again!
Tested with size optimisation - no noticeable difference…
I replaced the ADC chip on my DSO which was showing abnormal CH(A) traces. Used an Analog Devices AD9288-80 chip which I purchased from Digikey.com.
The old ADC chip was the same as yours; markings were difficult to read, but appeared to be HWD9288BSTZ-40.
Attached, are screenshots of BEFORE and AFTER ADC chip upgrade with WC5.1 and FPGA V1.1 installed. Screenshots for “full speed oversampling” and “normal buffer” modes.
Thanks again for the feedback. I think the results speak for themselves.
For those with issues with their DAC using V5.1 and it’s FPGA with HW 2.81 an alternative would be to use the FPGA supplied with V5.0 . This should work fine with V5.1 and HW 2.81 with the problem DAC’s, and while it would not have full speed sampling, it would provide improved level based triggering accuracy and overall triggering stability at the fastest timebases over the factory FPGA. It would also provide auto mode freerun behavior selection.
A few days ago I ordered a DSO202, but something went wrong with the order. This will be fixed soon, but I’m now thinking of cancelling the order to get this DSO203 instead.
Its price is a bit higher, but I think it might be worth it.
I haven’t owned an oscilloscope for 30 years now, but would like to have one again. If I’m getting much more “bang for the buck” with this one I will cancel that order of the DSO202.
I didn’t know anything about a custom firmware like this one.
Is there one for the DSO202…
I would love to get some input before that order goes through…
Thanks
Frater,
DSO203 has many custom firmwares to try out. 4 channels to work with. Bandwidth is much better.
My choice is DSO203.
Jerson
I appreciate your reply and I know it’s somewhat off-topic, but I had no time to research it.
It seems my order for the Nano is now cancelled and I can order this DSO203.
The order needed cancelling anyhow, even if I still took that DSO202
It does seem to be a much newer device (the touch), but I think
Another question.
They speak of 2 analog channels and 2 digital channels on this one.
The dso202 has 2 analog channels, does it?
The touch 202 is a newer device and has good eyecandy but less analog bandwidth. However, I can swear by the DSO203 I own for a some time now. If you need more info, please open another thread so as not to divert this thread topic.
Hi, WildCat! I want to thank you for excellent operation and to wish a good health!
I updated the DSO203(HW 2.81 SYS1.64 DCU 3.43) on version 5.1 and used FPGA 1.1. I checked operation of an oscillograph in the mode of the complete buffer. Results are visible on a photo. Problems begin in the AC1V,AC2V,AC5V mode. In channel B there are no such problems.
Thanks for the feedback.
This is not an issue with the ADC. This is noise picked up by the preamp. Noise from the ADC would show up the same on the screen regardless of the vertical range used.
I had a similar problem with my unit, causing thickening of the trace on ChA in full speed mode similar to yours. Turned out to be a bad ground. The metal frame that holds the LCD is grounded by a stick-on metalized tape to one of the input or generator output jacks and it was making an intermittent connection. You could move the plugs around when inserted into the jacks and the noise would cut in and out.
In any case, this is definitively noise picked up by the front end in the input section. The device switches in a different op-amp when set to ranges of 1V/div and above. Looks to me like noise from the rest of the circuitry is being leaked into that section, possibly from a bad ground, capacitive coupling, power supply issues, etc… ChA seems more susceptible to this for some reason, probably because of the location of the circuit traces on the board. The LCD is also a prime cause of radiation into the circuitry if it’s frame is not properly grounded, since it covers the entire board. The grounding method is rather poor, relying on simple pressure of part of the frame onto the metalized stick-on tape.
As I mentioned previously, the full speed mode will, by it’s more sensitive nature more readily reveal any noise, whether generated by the circuit you are monitoring or generated inside the scope itself. This is in fact part of what makes it useful. Also, loose or defective probe plugs making a poor ground connection where inserted into the input jacks can cause problems like this.
You could try reverting to an earlier FPGA, it’s possible the extra circuitry for the full speed mode is causing an increase of noise on the supply lines, and an increase in this noise, but since it’s only appearing on some of the ranges, I suspect that some hardware issue in the preamp is causing this, and that it would also show up with earlier FPGA’s, though possibly to a lesser extent. Notice that the “spike” part of the noise shows up in your screenshots even when not in full speed mode.
Hi, Wildcat! Thanks for the detailed answer, I have understood you. It is interesting whether other owners of this version have such effect?
Prompt how you have solved a problem with grounding of LCD?
Hello Wildcat,
it seems there is an error in setting the trigger level.
If I select the trigger level for chan A and select level with button 4 I can lower the level with the left toggle,
but if I want to increase the level with the left toggle it just cycles through the sub-options as if pressing
button 4!
I am using your version 5.1 wit hardware 2.81 and the FPGA W1.1 file recommended for that version.
Then, after selecting something else the setting even refuses to go to the LEV section while pressing
button 4.
Any idea?
Best regards DK8HI
DK8HI,
The trigger LEV function is so commonly used, others with your hardware version and WC5.1 would have reported that weeks ago. Also doesn’t sound like a mechanical switch problem.
Try reloading your SYS & WC5.1, one at a time, to see if that issue is resolved by a reload.
You have to take the unit apart, of course. On the front side of the board, the frame of the LCD presses against a small wire mesh covered square that is glued to the Gen Out jack body. I first tried to solder a wire directly from ground to the LCD frame but the metal it was made out of didn’t seem solderable. I was reluctant to apply too much heat for fear of cracking or otherwise damaging the display, so I just soldered a piece of thin copper over the wire mesh and onto the jack which built up the thickness and allowed for a better contact with the LCD frame.
I just looked at pictures of some earlier hardware versions, and these seem to ground the LCD frame in a different location. There appears to be more than one display version being used, so not all units may be the same.
The only thing I can think of is maybe you have inadvertently pressed button 2, which sets the trigger level to AUTO. In this mode, cycling though the trigger menu with button 4, the “LEV” sub menu will be skipped. Press and HOLD button 2 until it beeps, this sets the trigger level to manual and moves the focus to the LEV sub menu. To the right of “LEV” will show “MAN”. In manual mode, button 4 can also be used to select LEV. When in auto level mode, MAN changes and cycles through 1/2, 3/4, then 1/4 with each SHORT press of button 2.
Good health to you, Wildcat! Recently bought a DSO DSO Quad. He wanted to update the firmware and searched the Internet, found. Before I HARDWARE was 2.81 and was 2.6. I do not understand what happened. Then set your firmware, it became much better. Can I create one that is not so. How to change the firmware properly? How to make CH(A) in the middle? When connected to a computer, he does not see it as a drive, format offers, but ends up formatting error. I am just learning. Help me please.
Photos from my mistakes DSO Quad could not upload here, but I can send them to you by mail.
Thanks!
Was not aware that button 2 would set auto trigger permanently.
DK8HI
You can send me a message. Explain what hardware version your DSO Quad is and what updates you have done.