Thanks again for the feedback. I think the results speak for themselves.
For those with issues with their DAC using V5.1 and it’s FPGA with HW 2.81 an alternative would be to use the FPGA supplied with V5.0 . This should work fine with V5.1 and HW 2.81 with the problem DAC’s, and while it would not have full speed sampling, it would provide improved level based triggering accuracy and overall triggering stability at the fastest timebases over the factory FPGA. It would also provide auto mode freerun behavior selection.