144M sampling is not currently implemented in the software. It’s supported in all FPGA versions, even very early ones. I set it up not too long ago to see how well it worked. It works but is extremely complex and tedious to set up, with special time bases, both time and level interlacing compensation needed and meters need to be adapted to it. It is only of any benefit at the 0.1uS/div timebase, since at 0.2 you need to halve the sampling rate so you might as well just use a non interleaved mode. The display is already pretty good at the ~10Mhz max anyways, not much to gain from such an elaborate function in my opinion.
The noise problem may have been there with previous FPGA’s, but the added gate functions, particularly the 32 bit compares for the time triggering makes it much worse, plus the nature of full speed sampling “records” every little blip, so it really shows up with that.
By a certain “level” I mean a level shift on the vertical display where some more significant bit takes over lesser ones (eg: shift from b01111 to b10000) . There was one such noise “spot” about 3/4 of the way up (actually this is 1/4 of the way up, since the FPGA inverts the input from the ADC) that acted different, seemed to always be there, even with the sampling rate reduced way down, while if a particular configuration otherwise created a lot of noise (at other “levels”), these would generally disappear below 18 or 9 MS/sec.
As far as the HWD9288 is concerned, I had to replace another one of those a couple of years back on another device that produced nothing but garbage on one channel at the 2 fastest timebases. And yes, I saw the photocopied data sheets… Pretty blatant of them!