DSO Quad bandwidth

Products & Technology DSO Quad
#64

Although I will refrain from further analog bandwidth discussions until I can conduct my own tests, I will not bad mouth the Quad analog bandwidth quality, until someone performs the following:

  1. Loads the current firmware
  2. Performs the published compensation adjustments
  3. Repeats the sinewave bandwidth tests with at least 1Mhz steps, while looking at the ADC input with a high quality scope.

I will do this when I get my replacement Quad. Until someone does all these things, the Quad analog bandwidth is still undefined.

Beta hardware replacement discussions are only valid once it has been determined that the firmware and adjustment procedures can not fix the problems. I don’t think we are there yet. Most things “beta” carry some level of frustration, so why should this be any different? Patience is a virtue that is hard to manage, yet necessary when dealing with “beta” products.

Bainsbunch has a previous post about “lightening up”, and I have to agree with that concept, even though it now appears that “lightening up” appears to have become road kill. Seeed Studio does not control those folks who write the firmware changes, so Seeed certainly can not expedite those updates. It would be most helpful though, if Seeed would confirm when forum issues and concerns have been presented to the manufacturer for action.

By the way, all the above is just my opinion, not factual representation, and is therefore not subject to argument.

#65

Whilst I am not qualified to make any technical input into this debate I have to say that Seeed have been conspicuously quiet on the subject.

I understand the risks of beta systems but when I signed up for the trials by investing my money I have, I believe, a reasonable expectation to see some response from the people who took my money.

One of the reasons for beta testing is to iron out issues like the ones being discussed in this thread and others issues in another thread about firmware improvements which incidentally are getting a response

This thread moved into a technical debate into the theory of what and how to test the units but has not addressed the post that started it all off and that was Seeed telling us that the unit was not coming up to specification.

All I am asking for is a statement from Seeed as to what , if anything, they are doing to address the issue they themselves brought to our attention.

“Lightening” the debate does not mean staying quiet and hopping that seeed will eventually speak up and say something.

Cheers Pete.

#66

For Bainesbunch: yes, my English is horrible, plus auto correct option => funny sentiences :slight_smile:

I mean to say that digital filters require more CPU work, so CPU uses more current (power consumption) which reduces battery life.

#67

See my May 14 post at viewtopic.php?f=22&t=2003

#68

I want to correct a previous post which is in error. Further examination of the FPGA (U6) caps C21 and C22, finds that I was mistaken when I thought both caps were 22ufd. Instead, both caps are connected in parallel and C22 is a 105 cap which will provide the necessary decoupling. I think my eyes crossed on that one.

#69

Ok, I decided to model the front end of the analog channels, which was done on Multisim.
DSOQ_FE_Schematic.jpg

Here are the results:

DSOQ_FE_F_Response.jpg
DSOQ_FE_Phase.jpg

The 3dB point for signal 1 about 700kHz and for signal 2 is about 200kHz.Looking at these large resistors in the front end the results do not surprise me actually – the RC constants are far stretch from minimized. The resistances in the op-amps feedback loops are also way too large to expect overall wide BW. Realistically the front end should be have been buffered and then scaled and sampled.
Keeping in mind that this simulation is assuming perfect conditions (no stray capacitance at the very least) I’d say that the front end needs some work, but this is just my 2c.

#70

If the gain resistors are reduced and front end optimized as is then theoretically one can get up to 10MHz overall flat response @ G=10 according to the OPA2354 datasheet which makes sense. The corrected circuit is shown below. The C9 and C11 10pF caps should be lifted as well as C7A. Feedback resistors should be reduced as much as possible while maintaining the necessary gain.

DSOQ_FE_Schematic_Single_Stage_Optimized.jpg

According to the plots these changes shift the 3dB point for both signals up to 12MHz which in reality is overly optimistic. I’d say 10MHz BW is more realistic but still hard to achieve as it is highly dependent on the PWB layout.

DSOQ_FE_F_Response_Single_Stage_Optimized.jpg
DSOQ_FE_Phase_Single_Stage_Optimized.jpg

#71

In order to achieve higher BW multiple smaller gain stages are needed. The example below shifts the cutoff to about 27MHz. I think I will try the first solution as it is fairly straight forward given the parts are not something smaller than 0805…
DSOQ_FE_Schematic_Dual_Stage_Optimized.jpg
DSOQ_FE_F_Response_Dual_Stage_Optimized.jpg
DSOQ_FE_Phase_Dual_Stage_Optimized.jpg

#72

Hi,

i also did the same simulation (i wasn’t aware of geshsoft ones) as geshsoft but with TINA-TI (Texas Instruments). And looking at the simulations i came with the same conclusions. Getting rid of C9, C11 & C73 (or at least use lower capacities) will improve the circuit performance. Also the use of small valued resistors (i.e. 2,7k instead of 27k and keeping the same ratio for others) will also improve bandwith (but that’s a few small resistors -16- to solder).

That said, the only fact that disturbs me from simulation is that i didn’t find the strange channel behaviour venarim described. I suppose this is due to the stray capacitances not modelled in simulator. Sooo, it would be interesting to know how accurate are this simple simulations in order to tweak the circuit.

I leave the circuit as an attachment just in case someone wants to play with it.
QUAD.zip (7.86 KB)

#73

Unfortunately simulators don’t tell the truth at these gain and frequency levels. The biggest problem would be getting stability and I suspect that C9 C11 and C73 were added later to acheive stability. Removing them is probably not an option. PCB layout is everything and having gain switching really makes the layout difficult because the + and - input nodes of the op amps need to be as short as possible. It should be possible to get 15nS rise time with the 27MHz circuit above but it will be difficult. Might be an idea to build up a simple fixed gain circuit first.

#74

Thanks for pointing out that the circuit board traces have resistance, inductance, and capacitance that can greatly affect these circuits. I also suspect that those caps were added through trial and error.

Is there any way to quickly determine if there is a ground plane layer on this board?

It would be interesting if we could find a v2.2 schematic to compare any differences in the front-end circuits.

#75

Yes, pick a powerfull light source and put the PCB in between the light and you. If you could not see through the PCB, then there is probably (could be a VCC one or other - but it’s very unlikely at best) a ground plane. :wink:

#76

I just tried removing C73 (33pF) and it made a remarkable difference to bandwidth on the 0.5v range of ch.A I am now getting -3dB sinewave response to 10MHz. I then used a good quality scope to check the squarewave response at U6, AIN and there was slight overshoot but no instability or ringing.

I have noticed that my DSO Quad will not trigger on timebase ranges of 0.2uS and 0.1uS when set for channel A only (ie. with all other channels in HIDE) Has anyone else seen this?

#77

Yes I agree with the fact that the simulation is just a rough approximate of the real world performance which is not accommodating for parasitics, and I did state so. The gerber files would be something I’d definitely want to see.

I opened up the scope yesterday and the R and C are definitely smaller than 0805, so I will order the parts I need to tweak the front end soon enough. I am planning on running a frequency sweep on the front end only and monitoring with my Tektronix - this way i won’t be limited by any firmware / software faults to properly determine what are its actual capabilities.

As far as slight overshoot - C37 is killing AC performance at higher frequencies just like C9, C11, C10 and C12 do. Removing the capacitors opens up the BW so the op-amp will perform closer to its specs which do show slight overshoot at the falling edge on the step response plot. The behavior is slightly worsened probably by parasitics. As bielec pointed out these capacitors were there as an afterthought or maybe even planned as space holders as compensation network which is fine. I have the feeling that the final values placed in our units did not get tested before hand however. In other words some fine tuning needs to be done to get the max benefit from this very simplified front end.

Like bielec I also noticed the triggering problem at 0.1us and 0.2us. Actually the signal fails to reconstruct properly on the screen once I exceed 2.3MHz or so. I will need to rerun all this once the analog BW is opened up.

#78

I removed C9 and C11. This allowed much better bandwidth but overshoot was present and it varied depending on the input voltage setting. So what is needed is a different overshoot trimming capacitor across each gain setting resistor. That is 6 capacitors for channel A across each of R13,R17,R21,R11,R15,R19. These could be soldered on top of the resistors when proper values are determined.

For the sake of the experiment, I made capacitors from two short lengths of thin teflon coated wire, twisted together and fitted these across the R’s. I acheived acceptable compensation on all ranges and got bandwidth up to about 10MHz with good pulse response enabling me to easily display a 100nS pulse with 20nS edges.

A note on the probe compensating capacitors is in order. For ch A. the influence of C3A and C5A interact depending on voltage setting, making setting up difficult. The method I used was to inject a 10KHz squarewave and adjust for best shape while switching between the 0.5v and 1v ranges.

#79

i am not so skillfull about the circirt , but i think, maybe you stimulation lacks a inportant item, the cpc1017 , which is not a wire when shorted, it contains a C about 30pF between the 2 legs in circuit , and also C between the 2 legs with the ground. that is what the designer (bure) told me, these C make the whole story different…

#80

As far as datasheet states, cpc1017 has 30pf parallel to the switch and 1pF between input/output. I included in the simulation and the effect is negligible at the opamp inputs in terms of gain. Probably it will affect in terms of overshoot.

I updated simulation circuit to reflect the changes.
QUAD v2.zip (8.12 KB)

#81

I have modified my scope to increase the bandwidth as follows…

For ch A.
Remove C73
C11=1.5pF
Across R17 3.3pF
Across R21 22pF
C9=1.5pF
Across R15 3.3pF
Across R19 12pF

For ch B.
Remove C74
C12=1.5pF
Across R18 2.2pF
Across R22 15pF
C10=1.5pF
Across R16 2.2pF
Across R20 12pF

I now get about 10MHz sinewave bandwidth on all ranges and good pulse response with minimal overshoot and rounding. Trigger and good display of sub 100nS pulses is now possible. As delivered, the scope had less than 1MHz B.W. and poor risetime which varied depending on range.

I would suggest the above values are used as a guide, for experimentation, and I hope it may help others get better performance.

#82

Greetings all,
I’ve been monitoring all your comments and investigating your data concerning the Quad bandwidth topic.

I ordered a Quad, but not received it yet.

I have the schematic, component datasheets, and have been using Slimfish’s “Quad.zip” file for analysys. Thanks Slimfish, you saved me the trouble.

This is my $.02

In my mind, the first logical step is the 72Ms/s sample rate issue.
I like lygra’s take on this and the sampling chart.
I personally would want an accurate graphical representation of a signal, otherwise, want’s the point?
My Instek GDS-1062A has a sample rate of 1Gs/s and 60MHz bandwidth.
With a 60MHz signal, that works out to 16 samples per cycle, and that many samples per cycle on the Quad would be for a 4.5MHz signal.
I don’t see the Quad being useful beyond 10MHz.

Now for the OPA2354 opamp issue.
With all range switches open, the amp has a gain of 10, the datasheet shows a small signal bandwidth f-3db = 10MHz at a gain of 10.
Also I noticed the power supplies are 3.6 and -3.0 which exceed the max specified voltage of 5.5V, but not the absolute max rating of 7.5V.
I’m wondering if this will effect the slew rates/bandwidth because operating a transistor close to breakdown voltage increases leakage current possibly causing slower response.

As far as testing an actual Quad, I have a scope and a Parallax Propeller proto-board, there is a demo for synthesizing square waves up to 120MHz

Tina-TI testing confirms a lot of what everyone has been saying.
I plan to modify Slimfish’s circuit to include a scope probe and function generator impedence.
I’m aware that spice programs don’t include parasitic signals and stray capacitance, Spice is for before/after picture, looking for improvement. The designer should know the limits of spice and compensate for it in the real world.

I’ll post more when I have more, Thanks

#83

Nice find on the op-amp supply voltage specifications. The Quad -3V comes from a non-regulated TC1221 which provides -5V light load, and slumps with more current draw. I want to confirm that it is -3V when I get my replacement Quad (supposedly next Monday according to DHL). I will also confirm the 3V6 voltage with a fully charged battery.