Bus faults with xiao nrf54l15?

Products & Technology XIAO
,
10

Hi there,

Fuzzing Awesome" thanks for getting back that it is running , so I posed the situation to them and I got some suggestions on the pin relocation.

first to, Keep UART21, but move it off SWO (advanced)

  • If you truly need uart21, remap it to non-SWO pins and ensure the board pinctrl + node reflect that; and/or disable SWO in your debug setup. Example (pick free pins that don’t clash):
&pinctrl {
	uart21_alt_default: uart21_alt_default {
		psels = <NRF_PSEL(UART_TX, 2, 4)>,  /* example: P2.4 */
		        <NRF_PSEL(UART_RX, 2, 2)>;  /* example: P2.2 */
		bias-pull-up;
	};
}

&uart21 {
	status = "okay";
	current-speed = <115200>;
	pinctrl-0 = <&uart21_alt_default>;
	pinctrl-names = "default";
};

…and make sure SWO/trace isn’t enabled on your probe.

With debug/logging on, use deferred logging and give stacks room; that prevents unrelated timing/ISR-logging crashes from muddying the waters:

CONFIG_LOG=y
CONFIG_LOG_MODE_IMMEDIATE=n
CONFIG_LOG_PROCESS_THREAD=y
CONFIG_LOG_DEFAULT_LEVEL=3
CONFIG_MAIN_STACK_SIZE=2048
CONFIG_ISR_STACK_SIZE=2048

(That’s the other failure mode you already suspected.) :+1:
On this board, uart21 uses P2.7 (SWO) by default. Disabling uart21 or switching your console to uart20 is the right move—and it’s what I’d standardize in the forum recipe.

This has lots of potential, I hope they get this and a few others sorted out quickly so they don’t lose the momentum. (software Lag) the Xiao line is big enough for a dedicated Software Seeedineer IMO. the project Developer seems to provide all support is probably why it is slowly coming out, I’m patient and confident. :yum:

HTH
GL :slight_smile: PJ :v:

They are looped in on ALL the finds too! :+1: