I’m not certain that I’m using the proper base address for the GPIO registers. In the esp32c6 technical manual I see the following:
7 IO MUX and GPIO Matrix (GPIO, IO MUX) GoBack
GPIO_FUNCn_OUT_SEL may be modified by the hardware. For such reason, it’s recommended to reconfigure
these registers when the GPIO is free from the control of ETM task channel.
GPIO has eight event channels, and the ETM events that each event channel can generate are:
• GPIO_EVT_CHx_RISE_EDGE: Indicates that the output signal of the corresponding GPIO filter (see Figure
7-1) has a rising edge;
• GPIO_EVT_CHx_FALL_EDGE: Indicates that the output signal of the corresponding GPIO filter (see
Figure 7-1) has a falling edge;
• GPIO_EVT_CHx_ANY_EDGE: Indicates that the output signal of the corresponding GPIO filter (see Figure
7-1) is reversed.
The specific configuration of the event channel is as follows:
• Set GPIO_EXT_ETM_CHx_EVENT_EN to enable event channel x (0 ~ 7).
• Configure GPIO_EXT_ETM_CHx_EVENT_SEL to y (0 ~ 30), i.e., select one from the 31 GPIOs.
Note:
One GPIO can be selected by one or more event channels.
In specific applications, GPIO ETM events can be used to trigger GPIO ETM tasks. For example, event channel
0 selects GPIO0, GPIO1 selects task channel 0, and the GPIO_EVT_CH0_RISE_EDGE event is used to trigger
the GPIO_TASK_CH0_TOGGLE task. When a square wave signal is input to the chip through GPIO0, the chip
outputs a square wave signal with a frequency divided by 2 through GPIO1.
7.15 Register Summary
7.15.1 GPIO Matrix Register Summary
The addresses in this section are relative to GPIO base address provided in Table 5-2 in Chapter 5 System and
Memory.
Then, in Table 5.2, I find the following entry:
GPIO Matrix 0x6009_1000
Does this seem like the correct base address for the set of GPIO registers?
Thanks again!