Bit-bang XIAO-ESP32C6 GPIO registers; processor rebooting

PJ_Glasso · May 25, 2025, 2:42pm

Hi there,

I like it, OLD school…

(Store Access Fault—)
The register addresses 0x3FF44008, etc., are for the ESP32 / ESP32S / ESP32-C3, not for the ESP32-C6.

The Boot loop , You set it to boot laoder mode to stop it (com port may change) reflash with a known good blink sketch

Why It Crashes:

On the ESP32C6:

Register addresses are different
You cannot directly reuse old ESP32 memory-mapped register tricks from ESP32/ESP32-S/C3
The C6 is based on RISC-V, and the GPIO peripheral base address changed

AL , has this code that is similar

#define GPIO_OUT_W1TS_REG 0x60004008
#define GPIO_OUT_W1TC_REG 0x6000400C
#define GPIO_ENABLE_W1TS_REG 0x60004024
#define GPIO_PIN 21

void setup() {
  volatile uint32_t* gpio_enable = (volatile uint32_t*)GPIO_ENABLE_W1TS_REG;
  volatile uint32_t* gpio_set = (volatile uint32_t*)GPIO_OUT_W1TS_REG;
  volatile uint32_t* gpio_clear = (volatile uint32_t*)GPIO_OUT_W1TC_REG;

  *gpio_enable = (1 << GPIO_PIN);   // Enable output
  *gpio_set = (1 << GPIO_PIN);      // Set HIGH
  delay(1000);
  *gpio_clear = (1 << GPIO_PIN);    // Set LOW
}

void loop() {}

The ESP32C6 is not register-compatible with the ESP32/ESP32S2/S3. Any direct memory access code from those chips must be revalidated against the new RISC-V register map.

Your right to learn bit-banging — but you’ve got to adjust for the silicon your on. Or use ESP-IDF macros if you want portable low-level access.

HTH
GL PJ