Thank you for providing some waveform analysis for this thread. Was the -3db roll-off used to determine 10Mhz analog bandwidth?
While looking at the schematic, U-5 and U-16, I noticed something that appears to be odd. C-21 and C-22 appear to provide a signal ground for the ADC /NOT inputs, yet there are no 105 decoupling capacitors for high frequencies. It is quite possible that these missing decoupling capacitors are contributing to the parasitic issues in the front-end circuits. This may also adversely affect the interleaved ADC operation. Correct me if I am wrong, but these ADC /NOT inputs must be high frequency decoupled if they are to represent signal ground plane. Looking back on the Nano V2 schematic, the ADC portion of the STM used unbalanced input, and the Vref was decoupled inside the STM. Here in the Quad we have the ADC Vref being applied via external traces to the ADC /NOT inputs without high frequency decoupling.
I do believe that this could be a smoking gun for the ADC interleave issues, and may also play a role in the parasitic issues.
--------------- correction edit 16May2011 -----------------------------------
Further examination of the FPGA (U6) caps C21 and C22, finds that I was mistaken when I thought both caps were 22ufd. Instead, both caps are connected in parallel and C22 is a 105 cap which will provide the necessary decoupling. I think my eyes crossed on that one.
I understand that English is not your primary language, but I have to say that you have communicated very well on this topic. I wish I could write in Chinese as well as you can in English.
Technically, you are being conservative with the sine wave signal. Both channels enabled, single channel bandwidth would probably be closer to 7Mhz sample band width (still 10Mhz analog bandwidth) in my opinion. But in real life, because the Quad does not support the SinX display function (it only connects sample points with straight lines), then your conservative value would provide a better looking sine wave that is displayed with straight line connection of the dots.
If the above 10Mhz analog bandwidth measurement that you made was based upon a -3db roll-off, and if the interlaced ADC operation were fixed, then you could get about 10Mhz bandwidth for one channel disabled and 144Mhz sample rate, of course the straight line display dot connections will distort. If the smoking gun fix above is implemented, then that may increase the front-end analog bandwidth above 10Mhz and that would increase the current 10Mhz limit.
As discussed previously in this post, the square wave is a different animal. As described earlier in this thread, the square wave corners are created by the odd order harmonics, and the first 3 odd harmonics are not sufficient to get a reasonable square wave. So the square wave sample bandwidth would be significantly lower to prevent rise time distortion of the square wave which results in the narrowing of the square wave into a sine wave appearance.
Having conducted similar waveform analysis on the Nano V2, I have found that 1/20th sample rate provides a reasonable display, but that display still has rise time issues because of the relationship of the rise time and the Nano sample time limit. These same DSO issues will also apply to the Quad in direct proportion. Therefore the Quad sample bandwidth for a square wave with short rise time will most likely be 72Mhz/20 = 3.6Mhz and 144Mhz/20= 7.2Mhz respectively. If the square wave rise time is longer, then the Quad display will look better.