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Re: DSO Quad bandwidth

Posted: Fri May 13, 2011 4:19 pm
by Bainesbunch
dejan.pavlovic wrote: <Snip> power constipation and additional ........ </Snip>

ROFLMAO please tell me you ment to say "power consumption"

Cheers Pete

Re: DSO Quad bandwidth

Posted: Fri May 13, 2011 8:01 pm
by vernarim
The worst part of this situation is the almost total silence about the Company.
It's a silence making lot of rumor...

HugeMan, would you explain what will be the future of (our) Quads (at least of mine)?

For anyone is reading at this message: I'll sell my Quad for a discounted price (having few weeks). Contact me privately.

Re: DSO Quad bandwidth

Posted: Fri May 13, 2011 8:35 pm
by Bainesbunch
vernarim wrote:For anyone is reading at this message: I'll sell my Quad for a discounted price (having few weeks). Contact me privately.

Actually if i recall correctly they (Seeed) offered to change our quads (Beta versions) for production versions once they had ironed all the faults out for the cost of the postage and price difference. Considering the debacle that this has turned out to be i would have thought that they (Seeed) would be trying very hard to do some damage limitation public relations by at least offer to change them free of charge once the are fixed.

They (Seeed) have after all mis sold us a device under the description and sale of goods acts where the item is clearly not as described.

Furthermore if you had bought one to measure signals over 10 meg then it is also not fit for purpose.


Cheers Pete.

Re: DSO Quad bandwidth

Posted: Fri May 13, 2011 9:07 pm
by lygra
Although I will refrain from further analog bandwidth discussions until I can conduct my own tests, I will not bad mouth the Quad analog bandwidth quality, until someone performs the following:

1. Loads the current firmware
2. Performs the published compensation adjustments
3. Repeats the sinewave bandwidth tests with at least 1Mhz steps, while looking at the ADC input with a high quality scope.

I will do this when I get my replacement Quad. Until someone does all these things, the Quad analog bandwidth is still undefined.

Beta hardware replacement discussions are only valid once it has been determined that the firmware and adjustment procedures can not fix the problems. I don't think we are there yet. Most things "beta" carry some level of frustration, so why should this be any different? Patience is a virtue that is hard to manage, yet necessary when dealing with "beta" products.

Bainsbunch has a previous post about "lightening up", and I have to agree with that concept, even though it now appears that "lightening up" appears to have become road kill. Seeed Studio does not control those folks who write the firmware changes, so Seeed certainly can not expedite those updates. It would be most helpful though, if Seeed would confirm when forum issues and concerns have been presented to the manufacturer for action.

By the way, all the above is just my opinion, not factual representation, and is therefore not subject to argument.

Re: DSO Quad bandwidth

Posted: Fri May 13, 2011 11:21 pm
by Bainesbunch
Whilst I am not qualified to make any technical input into this debate I have to say that Seeed have been conspicuously quiet on the subject.

I understand the risks of beta systems but when I signed up for the trials by investing my money I have, I believe, a reasonable expectation to see some response from the people who took my money.

One of the reasons for beta testing is to iron out issues like the ones being discussed in this thread and others issues in another thread about firmware improvements which incidentally are getting a response

This thread moved into a technical debate into the theory of what and how to test the units but has not addressed the post that started it all off and that was Seeed telling us that the unit was not coming up to specification.

All I am asking for is a statement from Seeed as to what , if anything, they are doing to address the issue they themselves brought to our attention.

"Lightening" the debate does not mean staying quiet and hopping that seeed will eventually speak up and say something.

Cheers Pete.

Re: DSO Quad bandwidth

Posted: Sat May 14, 2011 6:19 pm
by dejan.pavlovic
For Bainesbunch: yes, my English is horrible, plus auto correct option => funny sentiences :)

I mean to say that digital filters require more CPU work, so CPU uses more current (power consumption) which reduces battery life.

Re: DSO Quad bandwidth

Posted: Sun May 15, 2011 8:45 am
by lygra
Bainesbunch wrote:"Lightening" the debate does not mean staying quiet and hopping that seeed will eventually speak up and say something.
See my May 14 post at ... =22&t=2003

Re: DSO Quad bandwidth

Posted: Tue May 17, 2011 12:20 am
by lygra
lygra wrote:Here in the Quad we have the ADC Vref being applied via external traces to the ADC /NOT inputs without high frequency decoupling. I do believe that this could be a smoking gun for the ADC interleave issues, and may also play a role in the parasitic issues.
I want to correct a previous post which is in error. Further examination of the FPGA (U6) caps C21 and C22, finds that I was mistaken when I thought both caps were 22ufd. Instead, both caps are connected in parallel and C22 is a 105 cap which will provide the necessary decoupling. I think my eyes crossed on that one.

Re: DSO Quad bandwidth

Posted: Wed May 18, 2011 3:06 am
by geshsoft
Ok, I decided to model the front end of the analog channels, which was done on Multisim.
Simplified schematic (replaced series components w/ equivalents)
DSOQ_FE_Schematic.jpg (62.56 KiB) Viewed 6388 times
Here are the results:
Frequency response
DSOQ_FE_F_Response.jpg (32.18 KiB) Viewed 6388 times
DSOQ_FE_Phase.jpg (32.21 KiB) Viewed 6388 times
The 3dB point for signal 1 about 700kHz and for signal 2 is about 200kHz.Looking at these large resistors in the front end the results do not surprise me actually – the RC constants are far stretch from minimized. The resistances in the op-amps feedback loops are also way too large to expect overall wide BW. Realistically the front end should be have been buffered and then scaled and sampled.
Keeping in mind that this simulation is assuming perfect conditions (no stray capacitance at the very least) I’d say that the front end needs some work, but this is just my 2c.

Re: DSO Quad bandwidth

Posted: Wed May 18, 2011 5:23 am
by geshsoft
If the gain resistors are reduced and front end optimized as is then theoretically one can get up to 10MHz overall flat response @ G=10 according to the OPA2354 datasheet which makes sense. The corrected circuit is shown below. The C9 and C11 10pF caps should be lifted as well as C7A. Feedback resistors should be reduced as much as possible while maintaining the necessary gain.
Optimized schematic
DSOQ_FE_Schematic_Single_Stage_Optimized.jpg (58.32 KiB) Viewed 6375 times
According to the plots these changes shift the 3dB point for both signals up to 12MHz which in reality is overly optimistic. I’d say 10MHz BW is more realistic but still hard to achieve as it is highly dependent on the PWB layout.
Frequency response
DSOQ_FE_F_Response_Single_Stage_Optimized.jpg (37.93 KiB) Viewed 6375 times
DSOQ_FE_Phase_Single_Stage_Optimized.jpg (33.58 KiB) Viewed 6375 times