DSO Quad bandwidth

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HugeMan
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Re: DSO Quad bandwidth

Post by HugeMan » Fri May 06, 2011 5:31 pm

ok, this afternoon , I tested the Quad , here is what i found.
1. what is the bandwidth of the analog input channel?
From the connector to U5_pin13 and U16 _pin13 ,it is 10M .
lots of reasons for this .for example, the parasitic capacity around the U5 and U16, it is very distinct.
2. what is the sample rate ?
The max sample rate is 72M/s when T/div is 0.1us. Although we are seeking to make the sample rate to 144M when the other channel is unenabled, but now ,it seems not work .
as in this picture , the signal is 5M. and you can see about 14 points in a period. so the sample rate is 72M ,and if the CHA was hiden, this wave mess up.
/.
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as the 10M signal , the gain becomes about -6db. so , i believe we can say the bandwidth is 5M now

vernarim
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Re: DSO Quad bandwidth

Post by vernarim » Fri May 06, 2011 8:12 pm

HugeMan, I don't know whether your Quad has the same hardware as the mine, but *of sure* the mine has a -3dB cutoff around 2-3MHz.
Please, specify whether the probe could be so relevant in the test, because I have considered it always in my tests.

I don't understand what you stated also: at the very beginning of your post you are saying that the analog bandwidth is 10MHz, then at the end you say is 5MHz. What is the correct value?
I'd love to detect a 10-15MHz of *real* bandwidth. It means inputting a 10MHz @1Vpp sine on the probe and reading around 700mVpp on the display. Being step-shaped, no matter if I read 700mVpp or 750mVpp. On my test I read a *supposed* 400mVpp!
If you have a Quad granting 10MHz of overall bandwidth, I'll swap with the mine as soon. I will pay the shipping charge also!

About the sampling rate, I have also detected 72Ms/s and it could be fully acceptable from my viewpoint.
Thanks.

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Re: DSO Quad bandwidth

Post by lygra » Fri May 06, 2011 9:31 pm

Slimfish wrote:Hi thanh & lygra,
thanh wrote:Why do they have to reduce the sample rate when they increase the time div?
Assume the buffer can store 4000 samples. When they reduce the time div (or increase the sample rate), they can still capture 4000 samples, and only need to display these 4000 samples. Obviously, this 4000 samples can only capture a shorter length of the signal, but on the screen we also has to display less because of smaller t div. Correct?
The buffer is used to compute avg, rms, dc, ac, frequency, period.... If your buffer is filled always at same sampling rate you'll lose a lot of precisión in those calculations. Besides, going from 0.1us/div to 1us/div and your buffer samples are just in the limit to fill the screen.
At the risk of insulting you, I disagree with everything you have said in these two sentences. I feel compelled to attack and destroy wild statements that dilute and disrupt positive and valid discussions. We are trying to keep these discussions factual and not based upon opinions. Please provide evidence that supports what you have said. Show us in the source code where these processes that you describe, take place, and what the display buffer has to do with sample rate. Or at a minimum show us some waveform analysis that supports your assertions.
Slimfish wrote:
thanh wrote:If we use 10x sample rate as standard, then 3.6MHz should be the bandwidth? or is it 1/10 of 15MHz that Hugeman was mentioning?
Analog bandwidth and sampling rate should not be mixed. Analog bandwidth is constant for all T/divs (the exact quantity is unknown to me, but about 2MHz -see previous posts-) at least in this scope. It defines the frequency at which the signal is attenuated by 3 dB. It works like a low pass filter.
I agree with your statement about separating analog bandwidth from DSO results (sample rate). But then you use the findings of DSO display to talk about 2Mhz bandwidth limit that was discussed in previous post. Cant do that here, cant use DSO results to talk about analog bandwidth.
Slimfish wrote:Obviously the signal has to be sampled adequately in order to display the signal properly. A 20x oversampled signal looks much better than a x10 one. But that has nothing to do with analog bandwidth.
Agree here also. This is a valid statement.
Slimfish wrote: Benf has already shown that with a 1 Msps (DSO V1), controlling the sampling interval and trigger, you could have higher signal resolution (equivalent sampling speeds higher than ADC maximum). All of this is possible if signal has some periodic pattern.
These are wild and unsubstantiated claims. BenF increased the capture buffer update rate by increasing the sample rate at the expense of decreasing the capture buffer size for each acquisition. This was done for situations where the T/Div sample rate being used was below the ADC max sample rate capability. BenF also never attempted to provide enhanced virtual sample rate for repeating pattern signals. Please stop posting made up thoughts which simply distract from these thread discussions.

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Re: DSO Quad bandwidth

Post by lygra » Fri May 06, 2011 10:37 pm

HugeMan wrote:ok, this afternoon , I tested the Quad , here is what i found.
1. what is the bandwidth of the analog input channel?
From the connector to U5_pin13 and U16 _pin13 ,it is 10M .
lots of reasons for this .for example, the parasitic capacity around the U5 and U16, it is very distinct.
Thank you for providing some waveform analysis for this thread. Was the -3db roll-off used to determine 10Mhz analog bandwidth?

While looking at the schematic, U-5 and U-16, I noticed something that appears to be odd. C-21 and C-22 appear to provide a signal ground for the ADC /NOT inputs, yet there are no 105 decoupling capacitors for high frequencies. It is quite possible that these missing decoupling capacitors are contributing to the parasitic issues in the front-end circuits. This may also adversely affect the interleaved ADC operation. Correct me if I am wrong, but these ADC /NOT inputs must be high frequency decoupled if they are to represent signal ground plane. Looking back on the Nano V2 schematic, the ADC portion of the STM used unbalanced input, and the Vref was decoupled inside the STM. Here in the Quad we have the ADC Vref being applied via external traces to the ADC /NOT inputs without high frequency decoupling.

I do believe that this could be a smoking gun for the ADC interleave issues, and may also play a role in the parasitic issues.

--------------- correction edit 16May2011 -----------------------------------
Further examination of the FPGA (U6) caps C21 and C22, finds that I was mistaken when I thought both caps were 22ufd. Instead, both caps are connected in parallel and C22 is a 105 cap which will provide the necessary decoupling. I think my eyes crossed on that one.
--------------------------------------------------------------------
HugeMan wrote:On 2. what is the sample rate ? The max sample rate is 72M/s when T/div is 0.1us. Although we are seeking to make the sample rate to 144M when the other channel is disabled, but now ,it seems not work . as in this picture , the signal is 5M. and you can see about 14 points in a period. so the sample rate is 72M ,and if the CHA was hiden, this wave mess up... as the 10M signal , the gain becomes about -6db. so , i believe we can say the bandwidth is 5M now
I understand that English is not your primary language, but I have to say that you have communicated very well on this topic. I wish I could write in Chinese as well as you can in English.

Technically, you are being conservative with the sine wave signal. Both channels enabled, single channel bandwidth would probably be closer to 7Mhz sample band width (still 10Mhz analog bandwidth) in my opinion. But in real life, because the Quad does not support the SinX display function (it only connects sample points with straight lines), then your conservative value would provide a better looking sine wave that is displayed with straight line connection of the dots.

If the above 10Mhz analog bandwidth measurement that you made was based upon a -3db roll-off, and if the interlaced ADC operation were fixed, then you could get about 10Mhz bandwidth for one channel disabled and 144Mhz sample rate, of course the straight line display dot connections will distort. If the smoking gun fix above is implemented, then that may increase the front-end analog bandwidth above 10Mhz and that would increase the current 10Mhz limit.

As discussed previously in this post, the square wave is a different animal. As described earlier in this thread, the square wave corners are created by the odd order harmonics, and the first 3 odd harmonics are not sufficient to get a reasonable square wave. So the square wave sample bandwidth would be significantly lower to prevent rise time distortion of the square wave which results in the narrowing of the square wave into a sine wave appearance.

Having conducted similar waveform analysis on the Nano V2, I have found that 1/20th sample rate provides a reasonable display, but that display still has rise time issues because of the relationship of the rise time and the Nano sample time limit. These same DSO issues will also apply to the Quad in direct proportion. Therefore the Quad sample bandwidth for a square wave with short rise time will most likely be 72Mhz/20 = 3.6Mhz and 144Mhz/20= 7.2Mhz respectively. If the square wave rise time is longer, then the Quad display will look better.
Last edited by lygra on Tue May 17, 2011 8:48 pm, edited 8 times in total.

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Re: DSO Quad bandwidth

Post by lygra » Fri May 06, 2011 10:48 pm

vernarim wrote:HugeMan, If you have a Quad granting 10MHz of overall bandwidth, I'll swap with the mine as soon. I will pay the shipping charge also! About the sampling rate, I have also detected 72Ms/s and it could be fully acceptable from my viewpoint.
Thanks.
Have you measured your bandwidth at U5 and U15 pin-3? HugeMan is not referring to displayed results. He is referring to the inputs to the unity gain op-amps that directly feed the ADC.
HugeMan wrote:ok, this afternoon , I tested the Quad , here is what i found.
HugeMan you should repeat your test looking at the op-amp output (input to ADC U-6, pins 3 and 11) because this is a low impedence signal path and will be less affected by parasitics. Unity gain op-amps provide low impedence output and that is why unity gain op-amps should always drive the ADC input pins.

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Re: DSO Quad bandwidth

Post by vernarim » Sat May 07, 2011 2:37 am

lygra wrote:Have you measured your bandwidth at U5 and U15 pin-3? HugeMan is not referring to displayed results. He is referring to the inputs to the unity gain op-amps that directly feed the ADC.
No, I didn't open my Quad yet.
Anyway it makes to me almost a nonsense by saying about the "analog BW to pin 13...". The pin 13 is the ADC input!
What else should we count?

OK, on the next week I will try to perform some other tests, even by opening the scope.
Cheers

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Re: DSO Quad bandwidth

Post by slimfish675 » Sat May 07, 2011 5:45 am

Hi lygra,

first of all, i want to apologize to you: my last post was not intended to be a tutorial, so i assumed most of the facts i presented were already known.
Slimfish wrote:The buffer is used to compute avg, rms, dc, ac, frequency, period
You can find it in Benf sourcecode (v3.0), function.c, line 402, function void Measure_Wave(void). If you don't know C, the function description is self explanatory :-).
Its also used to help with trigger position (i.e. if trigger is in the middle of screen some points have to be sampled before trigger), signal panning and zoom.
Slimfish wrote:Besides, going from 0.1us/div to 1us/div and your buffer samples are just in the limit to fill the screen.
Supposing each pixel is a sample (to oversimplify things) in 0.1us/div and the screen uses 320 pixels for the signal, at 1us/div you will need 3200 samples (using only 1 out of 10) at the same sampling speed to complete the screen. Hence the "just in the limit" of the buffer.
Of course, you can use maximum sample rate even for 10s/div, you only have to decimate signal properly.
lygra wrote:At the risk of insulting you, I disagree with everything you have said in these two sentences. I feel compelled to attack and destroy wild statements that dilute and disrupt positive and valid discussions. We are trying to keep these discussions factual and not based upon opinions.
unlike you I don't feel compelled to destroy and attack anything. I'm more the kind of make the love and not the war :-). But lygra, a forum is a place to post opinions (and when possible facts) in order to discuss them.
lygra wrote:
Slimfish wrote: Benf has already shown that with a 1 Msps (DSO V1), controlling the sampling interval and trigger, you could have higher signal resolution (equivalent sampling speeds higher than ADC maximum). All of this is possible if signal has some periodic pattern.
These are wild and unsubstantiated claims.
As the source code is closed, only Benf can throw some light over this. But i agree with you that's irrelevant to the QUAD Bandwidth. My intention was to show that sampling speed is not a key factor if you have enough analog bandwidth. Most cheap scopes use that.
Check this: http://cp.literature.agilent.com/litweb ... 8794EN.pdf
lygra wrote:Please stop posting made up thoughts which simply distract from these thread discussions.
WTF? I'm used to post things i'm pretty sure of. My post was an answer to questions posed by Thanh and not solved by you.
And excuse me again, i wasn't aware that i was distracting you. You have to focus yourself a little ;-)

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Re: DSO Quad bandwidth

Post by lygra » Sat May 07, 2011 10:00 am

vernarim wrote:
lygra wrote:Have you measured your bandwidth at U5 and U15 pin-3? HugeMan is not referring to displayed results. He is referring to the inputs to the unity gain op-amps that directly feed the ADC.
No, I didn't open my Quad yet.
My point was that you are comparing apples to oranges. DSO display results are never the proper way to measure analog bandwidth for all the reasons already posted in this thread. Looking forward to your findings when you do open it up, as validation of HugeMan's findings.

Thanks

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Re: DSO Quad bandwidth

Post by lygra » Sat May 07, 2011 10:06 am

Slimfish; Ok, so everything you say is correct and I with my unlimited misconceptions, stand corrected.

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Re: DSO Quad bandwidth

Post by lygra » Sun May 08, 2011 1:08 am

vernarim wrote:For example, let's consider a 1MHz perfect square wave. The main sine wave is at 1MHz, of course, and it is the greater in amplitude. It has a 3rd harmonic, whose amplitude is about 1/3 the main. Then there is the 5th, having 1/5 of amplitude, etc. If the scope would had a 15MHz of BW (as HugeMan is going to do), then I would have attenuations over the 13-15th harmonic...my wave would be a good square anyway. Since I do NOT see that and I see a oddly shaped wave, I'd suppose the BW is much slower.
I finally found time to research this topic some more. There appears to be a mistake in your calculations here. The first and subsequent odd harmonics for a 1Mhz square wave would be 3,5,7,9,11,13,15,17,19,21,23,25 and 27Mhz to pass the 13th odd order harmonic.

Anything over the sixth odd harmonic of this 1Mhz square wave will be at or greater than -3db attenuation due to the 15Mhz DSO Quad analog bandwidth, so a poor waveform is to be expected because of analog bandwidth limiting.

Another assertion claimed by you and others is that the Nyquist theory only requires 2x of the signal for a sampling rate. You failed to include the rest of that definition which says "a signal must be sampled at least twice as fast as it's highest frequency component." With the square wave this would require many odd order harmonics, so in your example above, to include the 13th odd harmonic, then you would require a sample rate of 54MSa/s to reproduce that 1Mhz square wave waveform accurately.

So even if the analog bandwidth could pass the 27Mhz harmonic (and it apparently can't), then the sample rate would still be destroyed according to Nyquist while using a 36MSa/s sample rate.

If you fall back and say, OK, lets just use a signal generator that can only output the 5th odd harmonic and we know that we will have a slower rise time (less than 10%) source signal waveform because of this harmonic limit. The fifth order odd harmonic of 1Mhz is 11Mhz so the DSO Quad bandwidth can pass this harmonic. According to Nyquist, with fifth harmonic (11Mhz) being the highest frequency component, then 22MSa/s should accurately reproduce the poor quality input signal square wave, and the DSO Quad will reproduce that signal with its 36MSa/s capability.

So, in the end you will get a poor display of a 5th order odd harmonic limited signal input because of the signal itself, and you will also get a poor display of the perfect square wave input because of DSO Quad limitations as described above. As I had mentioned in my earlier posts, my poor quality function generator square wave signal looked pretty good on the DSO Quad because it didn't have enough odd harmonics present to add the DSO artifacts when the DSO Quad capability is exceeded. When I said it looked reasonable, it did look nearly as good as the input signal with some limited sampling artifacts which resulted in narrowed alternations (10% narrowing at the alternation tops). In the same write up, I also stated that the DSO Quad signal generator signal looked terrible, and now this can be attributed to my other statement about the generator signal looking like a very good square wave up to 8Mhz (which means it has lots of odd harmonics present) on a more expensive o'scope.

The attachments further clarify the above paragraph. You can see that the rise time for the 2nd odd harmonic waveform is about 6% (less than 10% rise time). So we will limit ourselves to the 2nd odd harmonic. This is 5 x 3.5Mhz = 17.5Mhz so it should get through the 15Mhz DSO Quad bandwidth with some amplitude fall off. I also mentioned in previous posts about some drooping of the tops and bottoms and this would indicate some kind of amplitude fall-off. According to Nyquist, the required sample rate would be 17.5Mhz x 2 = 35MSa/s. These numbers clearly show that I could in fact see the 10% rise time 3.5Mhz signal on the DSO Quad (with some amplitude distortion which I never measured).

Now lets look at a 3.5Mhz perfect square wave by your definition (13th odd harmonic is present). 3.5Mhz x 27 = 94.5Mhz analog bandwidth requirement and will not do well with a 15Mhz DSO Quad bandwidth limit. For the same perfect square wave, the Nyquist sampling rate would be 94.5Mhz x 2 = 189MSa/s so that wont happen either. This is why you can't look at the DSO Quad generator 2Mhz or 4Mhz square wave outputs on the DSO Quad display. It has nothing to do with the DSO Quad being defective, but is simply the result of the DSO signal sampling process while sampling a short rise time square wave.

In summary, in my first post in this thread I stated what I had observed but failed to talk about rise time as a factor for display results. Then Venarim in his first post stated that he didn't believe that I saw that. And then the thread just rambled on. It is my intention that this post will set the record straight and also explain the reason for differing observations between Venarim and myself.

It also might be pointed out here in the bandwidth discussion, that if the DSO Quad design had a hardware trigger circuit (and it does not) then for repeating waveforms, the firmware could be designed for equivalent time sampling with a magnitude order increase in the maximum observable waveform frequency. That would have made a tremendous improvement to the DSO Quad, but that approach was never taken during the design leap from the Nano to the Quad.

My reference for this post is http://www.cbtricks.com/miscellaneous/t ... mpling.pdf which is a Tektronics application note for Sampling Oscilloscopes.
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