DSO Quad bandwidth

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geshsoft
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Re: DSO Quad bandwidth

Post by geshsoft » Wed May 18, 2011 5:29 am

In order to achieve higher BW multiple smaller gain stages are needed. The example below shifts the cutoff to about 27MHz. I think I will try the first solution as it is fairly straight forward given the parts are not something smaller than 0805…
DSOQ_FE_Schematic_Dual_Stage_Optimized.jpg
Dual stage schematic
DSOQ_FE_Schematic_Dual_Stage_Optimized.jpg (87.22 KiB) Viewed 7244 times
DSOQ_FE_F_Response_Dual_Stage_Optimized.jpg
Frequency response dual stage
DSOQ_FE_F_Response_Dual_Stage_Optimized.jpg (73.73 KiB) Viewed 7244 times
DSOQ_FE_Phase_Dual_Stage_Optimized.jpg
Phase
DSOQ_FE_Phase_Dual_Stage_Optimized.jpg (35.19 KiB) Viewed 7244 times

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slimfish675
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Re: DSO Quad bandwidth

Post by slimfish675 » Wed May 18, 2011 4:24 pm

Hi,

i also did the same simulation (i wasn't aware of geshsoft ones) as geshsoft but with TINA-TI (Texas Instruments). And looking at the simulations i came with the same conclusions. Getting rid of C9, C11 & C73 (or at least use lower capacities) will improve the circuit performance. Also the use of small valued resistors (i.e. 2,7k instead of 27k and keeping the same ratio for others) will also improve bandwith (but that's a few small resistors -16- to solder).

That said, the only fact that disturbs me from simulation is that i didn't find the strange channel behaviour venarim described. I suppose this is due to the stray capacitances not modelled in simulator. Sooo, it would be interesting to know how accurate are this simple simulations in order to tweak the circuit.

I leave the circuit as an attachment just in case someone wants to play with it.
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QUAD.zip
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bielec
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Re: DSO Quad bandwidth

Post by bielec » Wed May 18, 2011 6:26 pm

Unfortunately simulators don't tell the truth at these gain and frequency levels. The biggest problem would be getting stability and I suspect that C9 C11 and C73 were added later to acheive stability. Removing them is probably not an option. PCB layout is everything and having gain switching really makes the layout difficult because the + and - input nodes of the op amps need to be as short as possible. It should be possible to get 15nS rise time with the 27MHz circuit above but it will be difficult. Might be an idea to build up a simple fixed gain circuit first.

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Re: DSO Quad bandwidth

Post by lygra » Wed May 18, 2011 9:00 pm

bielec wrote:PCB layout is everything and having gain switching really makes the layout difficult because the + and - input nodes of the op amps need to be as short as possible.
Thanks for pointing out that the circuit board traces have resistance, inductance, and capacitance that can greatly affect these circuits. I also suspect that those caps were added through trial and error.

Is there any way to quickly determine if there is a ground plane layer on this board?

It would be interesting if we could find a v2.2 schematic to compare any differences in the front-end circuits.

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Re: DSO Quad bandwidth

Post by slimfish675 » Wed May 18, 2011 9:30 pm

lygra wrote:Is there any way to quickly determine if there is a ground plane layer on this board?
Yes, pick a powerfull light source and put the PCB in between the light and you. If you could not see through the PCB, then there is probably (could be a VCC one or other - but it's very unlikely at best) a ground plane. ;-)

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Re: DSO Quad bandwidth

Post by bielec » Wed May 18, 2011 10:59 pm

I just tried removing C73 (33pF) and it made a remarkable difference to bandwidth on the 0.5v range of ch.A I am now getting -3dB sinewave response to 10MHz. I then used a good quality scope to check the squarewave response at U6, AIN and there was slight overshoot but no instability or ringing.

I have noticed that my DSO Quad will not trigger on timebase ranges of 0.2uS and 0.1uS when set for channel A only (ie. with all other channels in HIDE) Has anyone else seen this?

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Re: DSO Quad bandwidth

Post by geshsoft » Thu May 19, 2011 12:02 am

Yes I agree with the fact that the simulation is just a rough approximate of the real world performance which is not accommodating for parasitics, and I did state so. The gerber files would be something I'd definitely want to see.

I opened up the scope yesterday and the R and C are definitely smaller than 0805, so I will order the parts I need to tweak the front end soon enough. I am planning on running a frequency sweep on the front end only and monitoring with my Tektronix - this way i won't be limited by any firmware / software faults to properly determine what are its actual capabilities.

As far as slight overshoot - C37 is killing AC performance at higher frequencies just like C9, C11, C10 and C12 do. Removing the capacitors opens up the BW so the op-amp will perform closer to its specs which do show slight overshoot at the falling edge on the step response plot. The behavior is slightly worsened probably by parasitics. As bielec pointed out these capacitors were there as an afterthought or maybe even planned as space holders as compensation network which is fine. I have the feeling that the final values placed in our units did not get tested before hand however. In other words some fine tuning needs to be done to get the max benefit from this very simplified front end.

Like bielec I also noticed the triggering problem at 0.1us and 0.2us. Actually the signal fails to reconstruct properly on the screen once I exceed 2.3MHz or so. I will need to rerun all this once the analog BW is opened up.

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Re: DSO Quad bandwidth

Post by bielec » Thu May 19, 2011 7:33 pm

I removed C9 and C11. This allowed much better bandwidth but overshoot was present and it varied depending on the input voltage setting. So what is needed is a different overshoot trimming capacitor across each gain setting resistor. That is 6 capacitors for channel A across each of R13,R17,R21,R11,R15,R19. These could be soldered on top of the resistors when proper values are determined.

For the sake of the experiment, I made capacitors from two short lengths of thin teflon coated wire, twisted together and fitted these across the R's. I acheived acceptable compensation on all ranges and got bandwidth up to about 10MHz with good pulse response enabling me to easily display a 100nS pulse with 20nS edges.

A note on the probe compensating capacitors is in order. For ch A. the influence of C3A and C5A interact depending on voltage setting, making setting up difficult. The method I used was to inject a 10KHz squarewave and adjust for best shape while switching between the 0.5v and 1v ranges.

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Re: DSO Quad bandwidth

Post by HugeMan » Thu May 19, 2011 9:20 pm

i am not so skillfull about the circirt , but i think, maybe you stimulation lacks a inportant item, the cpc1017 , which is not a wire when shorted, it contains a C about 30pF between the 2 legs in circuit , and also C between the 2 legs with the ground. that is what the designer (bure) told me, these C make the whole story different..

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Re: DSO Quad bandwidth

Post by slimfish675 » Thu May 19, 2011 9:52 pm

HugeMan wrote:i am not so skillfull about the circirt , but i think, maybe you stimulation lacks a inportant item, the cpc1017 , which is not a wire when shorted, it contains a C about 30pF between the 2 legs in circuit, and also C between the 2 legs with the ground. that is what the designer (bure) told me, these C make the whole story different..
As far as datasheet states, cpc1017 has 30pf parallel to the switch and 1pF between input/output. I included in the simulation and the effect is negligible at the opamp inputs in terms of gain. Probably it will affect in terms of overshoot.

I updated simulation circuit to reflect the changes.
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QUAD v2.zip
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