Search found 50 matches

by slimfish675
Mon May 23, 2011 4:04 pm
Forum: DSO
Topic: DSO Quad bandwidth
Replies: 117
Views: 124693

Re: DSO Quad bandwidth

Hi, Bielec, twisted wires as small capacitors... that's a very neat trick (also an old school one :-)). Good work!!! My question (as you are very handy with hw) is whether using small valued resistors could avoid the use of the three compensation capacitors... (as in U17). Other thing is if you have...
by slimfish675
Thu May 19, 2011 9:52 pm
Forum: DSO
Topic: DSO Quad bandwidth
Replies: 117
Views: 124693

Re: DSO Quad bandwidth

i am not so skillfull about the circirt , but i think, maybe you stimulation lacks a inportant item, the cpc1017 , which is not a wire when shorted, it contains a C about 30pF between the 2 legs in circuit, and also C between the 2 legs with the ground. that is what the designer (bure) told me, the...
by slimfish675
Wed May 18, 2011 9:30 pm
Forum: DSO
Topic: DSO Quad bandwidth
Replies: 117
Views: 124693

Re: DSO Quad bandwidth

Is there any way to quickly determine if there is a ground plane layer on this board? Yes, pick a powerfull light source and put the PCB in between the light and you. If you could not see through the PCB, then there is probably (could be a VCC one or other - but it's very unlikely at best) a ground...
by slimfish675
Wed May 18, 2011 4:24 pm
Forum: DSO
Topic: DSO Quad bandwidth
Replies: 117
Views: 124693

Re: DSO Quad bandwidth

Hi, i also did the same simulation (i wasn't aware of geshsoft ones) as geshsoft but with TINA-TI (Texas Instruments). And looking at the simulations i came with the same conclusions. Getting rid of C9, C11 & C73 (or at least use lower capacities) will improve the circuit performance. Also the use o...
by slimfish675
Fri May 13, 2011 5:41 am
Forum: DSO
Topic: DSO Quad bandwidth
Replies: 117
Views: 124693

Re: DSO Quad bandwidth

Hi lygra, Briefly: 1. ADC has no trigger. As far as i know, none of them have (in the sense of start a conversion when reaching a predefined limit). 2. A FPGA is a very complex device. It's advantage comes from its versatility in implementing digital logic which can run to 100's of MHz. It can imple...
by slimfish675
Thu May 12, 2011 4:41 pm
Forum: DSO
Topic: DSO Quad bandwidth
Replies: 117
Views: 124693

Re: DSO Quad bandwidth

Hi, i don't have much time now, so i have to be very brief. In process.h (APP code) is where the function Update_trig (trigger update) is. In the very first lines, __Set function is used to set parameters.. how?, in BIOS.h are the definitions. At some point in the file, you could see that some param...
by slimfish675
Wed May 11, 2011 5:03 pm
Forum: DSO
Topic: DSO Quad bandwidth
Replies: 117
Views: 124693

Re: DSO Quad bandwidth

I never talked about the fifth harmonic, I only referred to the 5th odd harmonic, not the same. If the first harmonic is even (2Mhz) then the pattern after the fundamental would be 2nd=even, 3rd=odd,4th=even,5th=odd; so the fifth harmonic would be odd and is 5Mhz, but I was referring to the second ...
by slimfish675
Mon May 09, 2011 7:00 pm
Forum: DSO
Topic: DSO Quad bandwidth
Replies: 117
Views: 124693

Re: DSO Quad bandwidth

Hi Lygra, I finally found time to research this topic some more. There appears to be a mistake in your calculations here. The first and subsequent odd harmonics for a 1Mhz square wave would be 3,5,7,9,11,13,15,17,19,21,23,25 and 27Mhz to pass the 13th odd order harmonic. sorry, but you're mistaken h...
by slimfish675
Sat May 07, 2011 5:45 am
Forum: DSO
Topic: DSO Quad bandwidth
Replies: 117
Views: 124693

Re: DSO Quad bandwidth

Hi lygra, first of all, i want to apologize to you: my last post was not intended to be a tutorial, so i assumed most of the facts i presented were already known. The buffer is used to compute avg, rms, dc, ac, frequency, period You can find it in Benf sourcecode (v3.0), function.c, line 402, functi...
by slimfish675
Fri May 06, 2011 3:59 pm
Forum: DSO
Topic: DSO Quad bandwidth
Replies: 117
Views: 124693

Re: DSO Quad bandwidth

Hi thanh & lygra, Why do they have to reduce the sample rate when they increase the time div? Assume the buffer can store 4000 samples. When they reduce the time div (or increase the sample rate), they can still capture 4000 samples, and only need to display these 4000 samples. Obviously, this 4000 ...